#define _S2IO_H
#define TBD 0
-#define BIT(loc) (0x8000000000000000ULL >> (loc))
+#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
#define SUCCESS 0
#define FAILURE -1
#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
+#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
#define S2IO_BIT_RESET 1
#define S2IO_BIT_SET 2
#define MAX_TX_FIFOS 8
#define MAX_RX_RINGS 8
+#define FIFO_DEFAULT_NUM 1
+
#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
u16 bus_speed;
+ int max_mc_addr; /* xena=64 herc=256 */
+ int max_mac_addr; /* xena=16 herc=64 */
+ int mc_start_offset; /* xena=16 herc=64 */
};
/* Structure representing MAC Addrs */
u64 List_Control;
#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
-#define TX_FIFO_FIRST_LIST BIT(14)
-#define TX_FIFO_LAST_LIST BIT(15)
+#define TX_FIFO_FIRST_LIST s2BIT(14)
+#define TX_FIFO_LAST_LIST s2BIT(15)
#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
-#define TX_FIFO_SPECIAL_FUNC BIT(23)
-#define TX_FIFO_DS_NO_SNOOP BIT(31)
-#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
+#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
+#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
+#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
};
/* Tx descriptor structure */
struct TxD {
u64 Control_1;
/* bit mask */
-#define TXD_LIST_OWN_XENA BIT(7)
-#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define TXD_LIST_OWN_XENA s2BIT(7)
+#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
-#define TXD_GATHER_CODE (BIT(22) | BIT(23))
-#define TXD_GATHER_CODE_FIRST BIT(22)
-#define TXD_GATHER_CODE_LAST BIT(23)
-#define TXD_TCP_LSO_EN BIT(30)
-#define TXD_UDP_COF_EN BIT(31)
-#define TXD_UFO_EN BIT(31) | BIT(30)
+#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
+#define TXD_GATHER_CODE_FIRST s2BIT(22)
+#define TXD_GATHER_CODE_LAST s2BIT(23)
+#define TXD_TCP_LSO_EN s2BIT(30)
+#define TXD_UDP_COF_EN s2BIT(31)
+#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
#define TXD_UFO_MSS(val) vBIT(val,34,14)
#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
u64 Control_2;
-#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
-#define TXD_TX_CKO_IPV4_EN BIT(5)
-#define TXD_TX_CKO_TCP_EN BIT(6)
-#define TXD_TX_CKO_UDP_EN BIT(7)
-#define TXD_VLAN_ENABLE BIT(15)
+#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
+#define TXD_TX_CKO_IPV4_EN s2BIT(5)
+#define TXD_TX_CKO_TCP_EN s2BIT(6)
+#define TXD_TX_CKO_UDP_EN s2BIT(7)
+#define TXD_VLAN_ENABLE s2BIT(15)
#define TXD_VLAN_TAG(val) vBIT(val,16,16)
#define TXD_INT_NUMBER(val) vBIT(val,34,6)
-#define TXD_INT_TYPE_PER_LIST BIT(47)
-#define TXD_INT_TYPE_UTILZ BIT(46)
+#define TXD_INT_TYPE_PER_LIST s2BIT(47)
+#define TXD_INT_TYPE_UTILZ s2BIT(46)
#define TXD_SET_MARKER vBIT(0x6,0,4)
u64 Buffer_Pointer;
struct RxD_t {
u64 Host_Control; /* reserved for host */
u64 Control_1;
-#define RXD_OWN_XENA BIT(7)
-#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define RXD_OWN_XENA s2BIT(7)
+#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
-#define RXD_FRAME_PROTO_IPV4 BIT(27)
-#define RXD_FRAME_PROTO_IPV6 BIT(28)
-#define RXD_FRAME_IP_FRAG BIT(29)
-#define RXD_FRAME_PROTO_TCP BIT(30)
-#define RXD_FRAME_PROTO_UDP BIT(31)
+#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
+#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
+#define RXD_FRAME_IP_FRAG s2BIT(29)
+#define RXD_FRAME_PROTO_TCP s2BIT(30)
+#define RXD_FRAME_PROTO_UDP s2BIT(31)
#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
*/
struct tx_curr_get_info tx_curr_get_info;
+ /* Per fifo lock */
+ spinlock_t tx_lock;
+
+ /* Per fifo UFO in band structure */
+ u64 *ufo_in_band_v;
+
struct s2io_nic *nic;
-};
+} ____cacheline_aligned;
/* Information related to the Tx and Rx FIFOs and Rings of Xena
* is maintained in this structure.
int in_use;
__be16 window;
u32 cur_tsval;
- u32 cur_tsecr;
+ __be32 cur_tsecr;
u8 saw_ts;
};
#define MAX_MAC_SUPPORTED 16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
- struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
+ struct mac_addr def_mac_addr[256];
struct net_device_stats stats;
int high_dma_flag;
atomic_t rx_bufs_left[MAX_RX_RINGS];
- spinlock_t tx_lock;
spinlock_t put_lock;
#define PROMISC 1
#define MAX_ADDRS_SUPPORTED 64
u16 usr_addr_count;
u16 mc_addr_count;
- struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
+ struct usr_addr usr_addrs[256];
u16 m_cast_flg;
u16 all_multi_pos;
volatile unsigned long state;
spinlock_t rx_lock;
u64 general_int_mask;
- u64 *ufo_in_band_v;
#define VPD_STRING_LEN 80
u8 product_name[VPD_STRING_LEN];
u8 serial_num[VPD_STRING_LEN];
/* Interrupt masks for the general interrupt mask register */
#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
-#define TXPIC_INT_M BIT(0)
-#define TXDMA_INT_M BIT(1)
-#define TXMAC_INT_M BIT(2)
-#define TXXGXS_INT_M BIT(3)
-#define TXTRAFFIC_INT_M BIT(8)
-#define PIC_RX_INT_M BIT(32)
-#define RXDMA_INT_M BIT(33)
-#define RXMAC_INT_M BIT(34)
-#define MC_INT_M BIT(35)
-#define RXXGXS_INT_M BIT(36)
-#define RXTRAFFIC_INT_M BIT(40)
+#define TXPIC_INT_M s2BIT(0)
+#define TXDMA_INT_M s2BIT(1)
+#define TXMAC_INT_M s2BIT(2)
+#define TXXGXS_INT_M s2BIT(3)
+#define TXTRAFFIC_INT_M s2BIT(8)
+#define PIC_RX_INT_M s2BIT(32)
+#define RXDMA_INT_M s2BIT(33)
+#define RXMAC_INT_M s2BIT(34)
+#define MC_INT_M s2BIT(35)
+#define RXXGXS_INT_M s2BIT(36)
+#define RXTRAFFIC_INT_M s2BIT(40)
/* PIC level Interrupts TODO*/
/* DMA level Inressupts */
-#define TXDMA_PFC_INT_M BIT(0)
-#define TXDMA_PCC_INT_M BIT(2)
+#define TXDMA_PFC_INT_M s2BIT(0)
+#define TXDMA_PCC_INT_M s2BIT(2)
/* PFC block interrupts */
-#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
+#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
/* PCC block interrupts. */
#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
static void s2io_rem_isr(struct s2io_nic * sp);
static void restore_xmsi_data(struct s2io_nic *nic);
+static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
+static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
+static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
+static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
+static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
+static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
static int
s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
projects / linux-2.6-omap-h63xx.git / blobdiff