r8169: more phy init for the 8168

[linux-2.6-omap-h63xx.git] / drivers / net / sky2.h

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 69cd98400fe669639b596ea99185d66e9b49e265..49ee264064ab85dc95ac522b93e72b8e240e7fa1 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -18,14 +18,6 @@ enum {
        PCI_CFG_REG_1   = 0x94,
 };
 
-enum {
-       PEX_DEV_CAP     = 0xe4,
-       PEX_DEV_CTRL    = 0xe8,
-       PEX_DEV_STA     = 0xea,
-       PEX_LNK_STAT    = 0xf2,
-       PEX_UNC_ERR_STAT= 0x104,
-};
-
 /* Yukon-2 */
 enum pci_dev_reg_1 {
        PCI_Y2_PIG_ENA   = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
@@ -151,38 +143,6 @@ enum pci_cfg_reg1 {
                               PCI_STATUS_REC_TARGET_ABORT | \
                               PCI_STATUS_PARITY)
 
-enum pex_dev_ctrl {
-       PEX_DC_MAX_RRS_MSK      = 7<<12, /* Bit 14..12: Max. Read Request Size */
-       PEX_DC_EN_NO_SNOOP      = 1<<11,/* Enable No Snoop */
-       PEX_DC_EN_AUX_POW       = 1<<10,/* Enable AUX Power */
-       PEX_DC_EN_PHANTOM       = 1<<9, /* Enable Phantom Functions */
-       PEX_DC_EN_EXT_TAG       = 1<<8, /* Enable Extended Tag Field */
-       PEX_DC_MAX_PLS_MSK      = 7<<5, /* Bit  7.. 5:  Max. Payload Size Mask */
-       PEX_DC_EN_REL_ORD       = 1<<4, /* Enable Relaxed Ordering */
-       PEX_DC_EN_UNS_RQ_RP     = 1<<3, /* Enable Unsupported Request Reporting */
-       PEX_DC_EN_FAT_ER_RP     = 1<<2, /* Enable Fatal Error Reporting */
-       PEX_DC_EN_NFA_ER_RP     = 1<<1, /* Enable Non-Fatal Error Reporting */
-       PEX_DC_EN_COR_ER_RP     = 1<<0, /* Enable Correctable Error Reporting */
-};
-#define  PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
-
-/* PEX_UNC_ERR_STAT     PEX Uncorrectable Errors Status Register (Yukon-2) */
-enum pex_err {
-       PEX_UNSUP_REQ   = 1<<20, /* Unsupported Request Error */
-
-       PEX_MALFOR_TLP  = 1<<18, /* Malformed TLP */
-
-       PEX_UNEXP_COMP  = 1<<16, /* Unexpected Completion */
-
-       PEX_COMP_TO     = 1<<14, /* Completion Timeout */
-       PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
-       PEX_POIS_TLP    = 1<<12, /* Poisoned TLP */
-
-       PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
-       PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
-};
-
-
 enum csr_regs {
        B0_RAP          = 0x0000,
        B0_CTST         = 0x0004,
@@ -419,7 +379,6 @@ enum {
                          Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
 
        Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
-                         Y2_IS_PCI_EXP |
                          Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
 };
 
@@ -1850,6 +1809,28 @@ enum {
 
 /*     GPHY_CTRL               32 bit  GPHY Control Reg (YUKON only) */
 enum {
+       GPC_TX_PAUSE    = 1<<30, /* Tx pause enabled (ro) */
+       GPC_RX_PAUSE    = 1<<29, /* Rx pause enabled (ro) */
+       GPC_SPEED       = 3<<27, /* PHY speed (ro) */
+       GPC_LINK        = 1<<26, /* Link up (ro) */
+       GPC_DUPLEX      = 1<<25, /* Duplex (ro) */
+       GPC_CLOCK       = 1<<24, /* 125Mhz clock stable (ro) */
+
+       GPC_PDOWN       = 1<<23, /* Internal regulator 2.5 power down */
+       GPC_TSTMODE     = 1<<22, /* Test mode */
+       GPC_REG18       = 1<<21, /* Reg18 Power down */
+       GPC_REG12SEL    = 3<<19, /* Reg12 power setting */
+       GPC_REG18SEL    = 3<<17, /* Reg18 power setting */
+       GPC_SPILOCK     = 1<<16, /* SPI lock (ASF) */
+
+       GPC_LEDMUX      = 3<<14, /* LED Mux */
+       GPC_INTPOL      = 1<<13, /* Interrupt polarity */
+       GPC_DETECT      = 1<<12, /* Energy detect */
+       GPC_1000HD      = 1<<11, /* Enable 1000Mbit HD */
+       GPC_SLAVE       = 1<<10, /* Slave mode */
+       GPC_PAUSE       = 1<<9, /* Pause enable */
+       GPC_LEDCTL      = 3<<6, /* GPHY Leds */
+
        GPC_RST_CLR     = 1<<1, /* Clear GPHY Reset */
        GPC_RST_SET     = 1<<0, /* Set   GPHY Reset */
 };
@@ -2050,20 +2031,19 @@ struct sky2_port {
 #ifdef CONFIG_SKY2_DEBUG
        struct dentry        *debugfs;
 #endif
-       struct net_device_stats net_stats;
-
 };
 
 struct sky2_hw {
        void __iomem         *regs;
        struct pci_dev       *pdev;
+       struct napi_struct   napi;
        struct net_device    *dev[2];
        unsigned long        flags;
 #define SKY2_HW_USE_MSI                0x00000001
 #define SKY2_HW_FIBRE_PHY      0x00000002
 #define SKY2_HW_GIGABIT                0x00000004
 #define SKY2_HW_NEWER_PHY      0x00000008
-#define SKY2_HW_RAMBUFFER      0x00000010      /* chip has RAM FIFO */
+#define SKY2_HW_FIFO_HANG_CHECK        0x00000010
 #define SKY2_HW_NEW_LE         0x00000020      /* new LSOv2 format */
 #define SKY2_HW_AUTO_TX_SUM    0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL  0x00000080      /* additional PHY power regs */
@@ -2147,25 +2127,4 @@ static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
        gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
        gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
 }
-
-/* PCI config space access */
-static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
-{
-       return sky2_read32(hw, Y2_CFG_SPC + reg);
-}
-
-static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
-{
-       return sky2_read16(hw, Y2_CFG_SPC + reg);
-}
-
-static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
-{
-       sky2_write32(hw, Y2_CFG_SPC + reg, val);
-}
-
-static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
-{
-       sky2_write16(hw, Y2_CFG_SPC + reg, val);
-}
 #endif