Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

[linux-2.6-omap-h63xx.git] / drivers / net / sky2.h

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index d63106cd74ba4184516a8117c88418fd5a927a79..92fb24b27d4577caab35b184c4e5d653439d45c6 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -28,6 +28,11 @@ enum pci_dev_reg_1 {
        PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
        PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
        PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
+
+       PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit  9.. 8:       GPHY Link Trigger Timer */
+       PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
+       PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
+       PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
 };
 
 enum pci_dev_reg_2 {
@@ -45,7 +50,11 @@ enum pci_dev_reg_2 {
 
 /*     PCI_OUR_REG_4           32 bit  Our Register 4 (Yukon-ECU only) */
 enum pci_dev_reg_4 {
-                                       /* (Link Training & Status State Machine) */
+                               /* (Link Training & Status State Machine) */
+       P_PEX_LTSSM_STAT_MSK    = 0x7fL<<25,    /* Bit 31..25:  PEX LTSSM Mask */
+#define P_PEX_LTSSM_STAT(x)    ((x << 25) & P_PEX_LTSSM_STAT_MSK)
+       P_PEX_LTSSM_L1_STAT     = 0x34,
+       P_PEX_LTSSM_DET_STAT    = 0x01,
        P_TIMER_VALUE_MSK       = 0xffL<<16,    /* Bit 23..16:  Timer Value Mask */
                                        /* (Active State Power Management) */
        P_FORCE_ASPM_REQUEST    = 1<<15, /* Force ASPM Request (A1 only) */
@@ -432,6 +441,7 @@ enum {
        CHIP_ID_YUKON_FE   = 0xb7, /* YUKON-2 FE */
        CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
        CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
+       CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
 };
 enum yukon_ec_rev {
        CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
@@ -454,6 +464,9 @@ enum yukon_ex_rev {
        CHIP_REV_YU_EX_A0    = 1,
        CHIP_REV_YU_EX_B0    = 2,
 };
+enum yukon_supr_rev {
+       CHIP_REV_YU_SU_A0    = 0,
+};
 
 
 /*     B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */