NEWEMAC: fix support for pause packets

[linux-2.6-omap-h63xx.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index f715b35dfd5457811811bccadd634ce544c441bd..3938eb35ce8cd479507131b3673ffa5e77dd8d96 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -109,7 +109,9 @@
 #define  CHIPREV_ID_5714_A2             0x9002
 #define  CHIPREV_ID_5906_A1             0xc001
 #define  CHIPREV_ID_5784_A0             0x5784000
+#define  CHIPREV_ID_5784_A1             0x5784001
 #define  CHIPREV_ID_5761_A0             0x5761000
+#define  CHIPREV_ID_5761_A1             0x5761001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -543,6 +545,8 @@
 #define  SG_DIG_FIBER_MODE              0x00008000
 #define  SG_DIG_REMOTE_FAULT_MASK       0x00006000
 #define  SG_DIG_PAUSE_MASK              0x00001800
+#define  SG_DIG_PAUSE_CAP               0x00000800
+#define  SG_DIG_ASYM_PAUSE              0x00001000
 #define  SG_DIG_GBIC_ENABLE             0x00000400
 #define  SG_DIG_CHECK_END_ENABLE        0x00000200
 #define  SG_DIG_SGMII_AUTONEG_TIMER     0x00000100
@@ -554,6 +558,11 @@
 #define  SG_DIG_AUTONEG_LOW_ENABLE      0x00000004
 #define  SG_DIG_REMOTE_LOOPBACK                 0x00000002
 #define  SG_DIG_LOOPBACK                0x00000001
+#define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
+                             SG_DIG_LOCAL_DUPLEX_STATUS | \
+                             SG_DIG_LOCAL_LINK_STATUS | \
+                             (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
+                             SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
 #define SG_DIG_STATUS                  0x000005b4
 #define  SG_DIG_CRC16_BUS_MASK          0xffff0000
 #define  SG_DIG_PARTNER_FAULT_MASK      0x00600000 /* If !MRADV_CRC16_SELECT */
@@ -874,7 +883,14 @@
 #define TG3_CPMU_HST_ACC               0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK       0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25       0x00130000
-/* 0x3620 --> 0x365c unused */
+/* 0x3620 --> 0x3630 unused */
+
+#define TG3_CPMU_CLCK_STAT             0x00003630
+#define  CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
+#define  CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
+#define  CPMU_CLCK_STAT_MAC_CLCK_12_5   0x00110000
+#define  CPMU_CLCK_STAT_MAC_CLCK_6_25   0x00130000
+/* 0x3634 --> 0x365c unused */
 
 #define TG3_CPMU_MUTEX_REQ             0x0000365c
 #define  CPMU_MUTEX_REQ_DRIVER          0x00001000
@@ -1715,6 +1731,12 @@
 #define MII_TG3_ISTAT                  0x1a /* IRQ status register */
 #define MII_TG3_IMASK                  0x1b /* IRQ mask register */
 
+#define MII_TG3_MISC_SHDW              0x1c
+#define MII_TG3_MISC_SHDW_WREN         0x8000
+#define MII_TG3_MISC_SHDW_APD_SEL      0x2800
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
+
 /* ISTAT/IMASK event bits */
 #define MII_TG3_INT_LINKCHG            0x0002
 #define MII_TG3_INT_SPEEDCHG           0x0004
@@ -2088,13 +2110,18 @@ struct tg3_link_config {
        u16                             speed;
        u8                              duplex;
        u8                              autoneg;
+       u8                              flowctrl;
+#define TG3_FLOW_CTRL_TX               0x01
+#define TG3_FLOW_CTRL_RX               0x02
 
        /* Describes what we actually have. */
-       u16                             active_speed;
+       u8                              active_flowctrl;
+
        u8                              active_duplex;
 #define SPEED_INVALID          0xffff
 #define DUPLEX_INVALID         0xff
 #define AUTONEG_INVALID                0xff
+       u16                             active_speed;
 
        /* When we go in and out of low power mode we need
         * to swap with this state.
@@ -2322,8 +2349,6 @@ struct tg3 {
 #define TG3_FLAG_EEPROM_WRITE_PROT     0x00001000
 #define TG3_FLAG_NVRAM                 0x00002000
 #define TG3_FLAG_NVRAM_BUFFERED                0x00004000
-#define TG3_FLAG_RX_PAUSE              0x00008000
-#define TG3_FLAG_TX_PAUSE              0x00010000
 #define TG3_FLAG_PCIX_MODE             0x00020000
 #define TG3_FLAG_PCI_HIGH_SPEED                0x00040000
 #define TG3_FLAG_PCI_32BIT             0x00080000
@@ -2378,6 +2403,7 @@ struct tg3 {
        u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS   0x00000001
 #define TG3_FLG3_ENABLE_APE            0x00000002
+#define TG3_FLG3_5761_5784_AX_FIXES    0x00000004
 
        struct timer_list               timer;
        u16                             timer_counter;