hso modem detect fix patch against Alan Cox'es tty tree

[linux-2.6-omap-h63xx.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index eba62e2074cad775909b51d0d7db33181ee7e007..8936edfb0438c992c6cf7ceeb8d6880aa0fa98fe 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -40,26 +40,11 @@
 #define  TG3PCI_DEVICE_TIGON3_4                 0x1647 /* BCM5703 */
 #define  TG3PCI_DEVICE_TIGON3_5761S     0x1688
 #define  TG3PCI_DEVICE_TIGON3_5761SE    0x1689
-#define TG3PCI_COMMAND                 0x00000004
-#define TG3PCI_STATUS                  0x00000006
-#define TG3PCI_CCREVID                 0x00000008
-#define TG3PCI_CACHELINESZ             0x0000000c
-#define TG3PCI_LATTIMER                        0x0000000d
-#define TG3PCI_HEADERTYPE              0x0000000e
-#define TG3PCI_BIST                    0x0000000f
-#define TG3PCI_BASE0_LOW               0x00000010
-#define TG3PCI_BASE0_HIGH              0x00000014
-/* 0x18 --> 0x2c unused */
-#define TG3PCI_SUBSYSVENID             0x0000002c
-#define TG3PCI_SUBSYSID                        0x0000002e
-#define TG3PCI_ROMADDR                 0x00000030
-#define TG3PCI_CAPLIST                 0x00000034
-/* 0x35 --> 0x3c unused */
-#define TG3PCI_IRQ_LINE                        0x0000003c
-#define TG3PCI_IRQ_PIN                 0x0000003d
-#define TG3PCI_MIN_GNT                 0x0000003e
-#define TG3PCI_MAX_LAT                 0x0000003f
-/* 0x40 --> 0x64 unused */
+#define  TG3PCI_DEVICE_TIGON3_57780     0x1692
+#define  TG3PCI_DEVICE_TIGON3_57760     0x1690
+#define  TG3PCI_DEVICE_TIGON3_57790     0x1694
+#define  TG3PCI_DEVICE_TIGON3_57720     0x168c
+/* 0x04 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL          0x00000068
@@ -110,10 +95,6 @@
 #define  CHIPREV_ID_5752_A1             0x6001
 #define  CHIPREV_ID_5714_A2             0x9002
 #define  CHIPREV_ID_5906_A1             0xc001
-#define  CHIPREV_ID_5784_A0             0x5784000
-#define  CHIPREV_ID_5784_A1             0x5784001
-#define  CHIPREV_ID_5761_A0             0x5761000
-#define  CHIPREV_ID_5761_A1             0x5761001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -131,6 +112,7 @@
 #define   ASIC_REV_5784                         0x5784
 #define   ASIC_REV_5761                         0x5761
 #define   ASIC_REV_5785                         0x5785
+#define   ASIC_REV_57780                0x57780
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -1202,6 +1184,8 @@
 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB  0x00002000
 #define  RDMAC_MODE_FIFO_SIZE_128       0x00020000
 #define  RDMAC_MODE_FIFO_LONG_BURST     0x00030000
+#define  RDMAC_MODE_IPV4_LSO_EN                 0x08000000
+#define  RDMAC_MODE_IPV6_LSO_EN                 0x10000000
 #define RDMAC_STATUS                   0x00004804
 #define  RDMAC_STATUS_TGTABORT          0x00000004
 #define  RDMAC_STATUS_MSTABORT          0x00000008
@@ -1648,6 +1632,12 @@
 #define  FLASH_5761VENDOR_ST_A_M45PE40  0x02000000
 #define  FLASH_5761VENDOR_ST_A_M45PE80  0x02000002
 #define  FLASH_5761VENDOR_ST_A_M45PE16  0x02000003
+#define  FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
+#define  FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
+#define  FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
+#define  FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
+#define  FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
+#define  FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
 #define  FLASH_5752PAGE_SIZE_256        0x00000000
 #define  FLASH_5752PAGE_SIZE_512        0x10000000
@@ -1655,6 +1645,7 @@
 #define  FLASH_5752PAGE_SIZE_2K                 0x30000000
 #define  FLASH_5752PAGE_SIZE_4K                 0x40000000
 #define  FLASH_5752PAGE_SIZE_264        0x50000000
+#define  FLASH_5752PAGE_SIZE_528        0x60000000
 #define NVRAM_CFG2                     0x00007018
 #define NVRAM_CFG3                     0x0000701c
 #define NVRAM_SWARB                    0x00007020
@@ -1747,6 +1738,17 @@
 #define TG3_NVM_DIRTYPE_SHIFT          24
 #define TG3_NVM_DIRTYPE_ASFINI         1
 
+#define TG3_EEPROM_SB_F1R0_EDH_OFF     0x10
+#define TG3_EEPROM_SB_F1R2_EDH_OFF     0x14
+#define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
+#define TG3_EEPROM_SB_F1R3_EDH_OFF     0x18
+#define TG3_EEPROM_SB_EDH_MAJ_MASK     0x00000700
+#define TG3_EEPROM_SB_EDH_MAJ_SHFT     8
+#define TG3_EEPROM_SB_EDH_MIN_MASK     0x000000ff
+#define TG3_EEPROM_SB_EDH_BLD_MASK     0x0000f800
+#define TG3_EEPROM_SB_EDH_BLD_SHFT     11
+
+
 /* 32K Window into NIC internal memory */
 #define NIC_SRAM_WIN_BASE              0x00008000
 
@@ -1921,12 +1923,6 @@
 #define MII_TG3_ISTAT                  0x1a /* IRQ status register */
 #define MII_TG3_IMASK                  0x1b /* IRQ mask register */
 
-#define MII_TG3_MISC_SHDW              0x1c
-#define MII_TG3_MISC_SHDW_WREN         0x8000
-#define MII_TG3_MISC_SHDW_APD_SEL      0x2800
-
-#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
-
 /* ISTAT/IMASK event bits */
 #define MII_TG3_INT_LINKCHG            0x0002
 #define MII_TG3_INT_SPEEDCHG           0x0004
@@ -1935,7 +1931,9 @@
 
 #define MII_TG3_MISC_SHDW              0x1c
 #define MII_TG3_MISC_SHDW_WREN         0x8000
-#define MII_TG3_MISC_SHDW_SCR5_SEL     0x1400
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
+#define MII_TG3_MISC_SHDW_APD_ENABLE   0x0020
 #define MII_TG3_MISC_SHDW_APD_SEL      0x2800
 
 #define MII_TG3_MISC_SHDW_SCR5_C125OE  0x0001
@@ -1943,9 +1941,8 @@
 #define MII_TG3_MISC_SHDW_SCR5_SDTL    0x0004
 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM  0x0008
 #define MII_TG3_MISC_SHDW_SCR5_LPED    0x0010
+#define MII_TG3_MISC_SHDW_SCR5_SEL     0x1400
 
-#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
-#define MII_TG3_MISC_SHDW_APD_ENABLE   0x0020
 
 #define MII_TG3_EPHY_TEST              0x1f /* 5906 PHY register */
 #define MII_TG3_EPHY_SHADOW_EN         0x80
@@ -2315,8 +2312,6 @@ struct tg3_link_config {
        u8                              duplex;
        u8                              autoneg;
        u8                              flowctrl;
-#define TG3_FLOW_CTRL_TX               0x01
-#define TG3_FLOW_CTRL_RX               0x02
 
        /* Describes what we actually have. */
        u8                              active_flowctrl;
@@ -2621,6 +2616,7 @@ struct tg3 {
 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
 #define TG3_FLG3_CLKREQ_BUG            0x00000800
 #define TG3_FLG3_PHY_ENABLE_APD                0x00001000
+#define TG3_FLG3_5755_PLUS             0x00002000
 
        struct timer_list               timer;
        u16                             timer_counter;
@@ -2652,10 +2648,9 @@ struct tg3 {
 
        /* PCI block */
        u32                             pci_chip_rev_id;
+       u16                             pci_cmd;
        u8                              pci_cacheline_sz;
        u8                              pci_lat_timer;
-       u8                              pci_hdr_type;
-       u8                              pci_bist;
 
        int                             pm_cap;
        int                             msi_cap;
@@ -2698,6 +2693,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCMAC131            0x143bc70
 #define TG3_PHY_ID_RTL8211C            0x001cc910
 #define TG3_PHY_ID_RTL8201E            0x00008200
+#define TG3_PHY_ID_BCM57780            0x03625d90
 #define TG3_PHY_OUI_MASK               0xfffffc00
 #define TG3_PHY_OUI_1                  0x00206000
 #define TG3_PHY_OUI_2                  0x0143bc00
@@ -2705,7 +2701,6 @@ struct tg3 {
 
        u32                             led_ctrl;
        u32                             phy_otp;
-       u16                             pci_cmd;
 
        char                            board_part_number[24];
 #define TG3_VER_SIZE 32