/*
* PHY functions
*
- * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
- * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
- * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
+ * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
*
*/
+#define _ATH5K_PHY
+
#include <linux/delay.h>
#include "ath5k.h"
{ 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
};
+/* RF2413/2414 mode-specific init registers */
+static const struct ath5k_ini_rf rfregs_2413[] = {
+ { 1, AR5K_RF_BUFFER_CONTROL_4,
+ /* mode b mode g mode gTurbo */
+ { 0x00000020, 0x00000020, 0x00000020 } },
+ { 2, AR5K_RF_BUFFER_CONTROL_3,
+ { 0x02001408, 0x02001408, 0x02001408 } },
+ { 3, AR5K_RF_BUFFER_CONTROL_6,
+ { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0xf0000000, 0xf0000000, 0xf0000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x03000000, 0x03000000, 0x03000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x40400000, 0x40400000, 0x40400000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x65050000, 0x65050000, 0x65050000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00420000, 0x00420000, 0x00420000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00b50000, 0x00b50000, 0x00b50000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00030000, 0x00030000, 0x00030000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00f70000, 0x00f70000, 0x00f70000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x009d0000, 0x009d0000, 0x009d0000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00220000, 0x00220000, 0x00220000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x04220000, 0x04220000, 0x04220000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00230018, 0x00230018, 0x00230018 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00280050, 0x00280050, 0x00280050 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x005000c3, 0x005000c3, 0x005000c3 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x0004007f, 0x0004007f, 0x0004007f } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000458, 0x00000458, 0x00000458 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x0000c000, 0x0000c000, 0x0000c000 } },
+ { 6, AR5K_RF_BUFFER_CONTROL_5,
+ { 0x00400230, 0x00400230, 0x00400230 } },
+ { 7, AR5K_RF_BUFFER,
+ { 0x00006400, 0x00006400, 0x00006400 } },
+ { 7, AR5K_RF_BUFFER,
+ { 0x00000800, 0x00000800, 0x00000800 } },
+ { 7, AR5K_RF_BUFFER_CONTROL_2,
+ { 0x0000000e, 0x0000000e, 0x0000000e } },
+};
+
+/* RF2425 mode-specific init registers */
+static const struct ath5k_ini_rf rfregs_2425[] = {
+ { 1, AR5K_RF_BUFFER_CONTROL_4,
+ /* mode g mode gTurbo */
+ { 0x00000020, 0x00000020 } },
+ { 2, AR5K_RF_BUFFER_CONTROL_3,
+ { 0x02001408, 0x02001408 } },
+ { 3, AR5K_RF_BUFFER_CONTROL_6,
+ { 0x00e020c0, 0x00e020c0 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x10000000, 0x10000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x002a0000, 0x002a0000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00100000, 0x00100000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00020000, 0x00020000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00730000, 0x00730000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00f80000, 0x00f80000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00e70000, 0x00e70000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00140000, 0x00140000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00910040, 0x00910040 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x0007001a, 0x0007001a } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00410000, 0x00410000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00810060, 0x00810060 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00020803, 0x00020803 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00000000, 0x00000000 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00001660, 0x00001660 } },
+ { 6, AR5K_RF_BUFFER,
+ { 0x00001688, 0x00001688 } },
+ { 6, AR5K_RF_BUFFER_CONTROL_1,
+ { 0x00000001, 0x00000001 } },
+ { 7, AR5K_RF_BUFFER,
+ { 0x00006400, 0x00006400 } },
+ { 7, AR5K_RF_BUFFER,
+ { 0x00000800, 0x00000800 } },
+ { 7, AR5K_RF_BUFFER_CONTROL_2,
+ { 0x0000000e, 0x0000000e } },
+};
/* Initial RF Gain settings for RF5112 */
static const struct ath5k_ini_rfgain rfgain_5112[] = {
{ AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
};
+/* Initial RF Gain settings for RF2413 */
+static const struct ath5k_ini_rfgain rfgain_2413[] = {
+ { AR5K_RF_GAIN(0), { 0x00000000 } },
+ { AR5K_RF_GAIN(1), { 0x00000040 } },
+ { AR5K_RF_GAIN(2), { 0x00000080 } },
+ { AR5K_RF_GAIN(3), { 0x00000181 } },
+ { AR5K_RF_GAIN(4), { 0x000001c1 } },
+ { AR5K_RF_GAIN(5), { 0x00000001 } },
+ { AR5K_RF_GAIN(6), { 0x00000041 } },
+ { AR5K_RF_GAIN(7), { 0x00000081 } },
+ { AR5K_RF_GAIN(8), { 0x00000168 } },
+ { AR5K_RF_GAIN(9), { 0x000001a8 } },
+ { AR5K_RF_GAIN(10), { 0x000001e8 } },
+ { AR5K_RF_GAIN(11), { 0x00000028 } },
+ { AR5K_RF_GAIN(12), { 0x00000068 } },
+ { AR5K_RF_GAIN(13), { 0x00000189 } },
+ { AR5K_RF_GAIN(14), { 0x000001c9 } },
+ { AR5K_RF_GAIN(15), { 0x00000009 } },
+ { AR5K_RF_GAIN(16), { 0x00000049 } },
+ { AR5K_RF_GAIN(17), { 0x00000089 } },
+ { AR5K_RF_GAIN(18), { 0x00000190 } },
+ { AR5K_RF_GAIN(19), { 0x000001d0 } },
+ { AR5K_RF_GAIN(20), { 0x00000010 } },
+ { AR5K_RF_GAIN(21), { 0x00000050 } },
+ { AR5K_RF_GAIN(22), { 0x00000090 } },
+ { AR5K_RF_GAIN(23), { 0x00000191 } },
+ { AR5K_RF_GAIN(24), { 0x000001d1 } },
+ { AR5K_RF_GAIN(25), { 0x00000011 } },
+ { AR5K_RF_GAIN(26), { 0x00000051 } },
+ { AR5K_RF_GAIN(27), { 0x00000091 } },
+ { AR5K_RF_GAIN(28), { 0x00000178 } },
+ { AR5K_RF_GAIN(29), { 0x000001b8 } },
+ { AR5K_RF_GAIN(30), { 0x000001f8 } },
+ { AR5K_RF_GAIN(31), { 0x00000038 } },
+ { AR5K_RF_GAIN(32), { 0x00000078 } },
+ { AR5K_RF_GAIN(33), { 0x00000199 } },
+ { AR5K_RF_GAIN(34), { 0x000001d9 } },
+ { AR5K_RF_GAIN(35), { 0x00000019 } },
+ { AR5K_RF_GAIN(36), { 0x00000059 } },
+ { AR5K_RF_GAIN(37), { 0x00000099 } },
+ { AR5K_RF_GAIN(38), { 0x000000d9 } },
+ { AR5K_RF_GAIN(39), { 0x000000f9 } },
+ { AR5K_RF_GAIN(40), { 0x000000f9 } },
+ { AR5K_RF_GAIN(41), { 0x000000f9 } },
+ { AR5K_RF_GAIN(42), { 0x000000f9 } },
+ { AR5K_RF_GAIN(43), { 0x000000f9 } },
+ { AR5K_RF_GAIN(44), { 0x000000f9 } },
+ { AR5K_RF_GAIN(45), { 0x000000f9 } },
+ { AR5K_RF_GAIN(46), { 0x000000f9 } },
+ { AR5K_RF_GAIN(47), { 0x000000f9 } },
+ { AR5K_RF_GAIN(48), { 0x000000f9 } },
+ { AR5K_RF_GAIN(49), { 0x000000f9 } },
+ { AR5K_RF_GAIN(50), { 0x000000f9 } },
+ { AR5K_RF_GAIN(51), { 0x000000f9 } },
+ { AR5K_RF_GAIN(52), { 0x000000f9 } },
+ { AR5K_RF_GAIN(53), { 0x000000f9 } },
+ { AR5K_RF_GAIN(54), { 0x000000f9 } },
+ { AR5K_RF_GAIN(55), { 0x000000f9 } },
+ { AR5K_RF_GAIN(56), { 0x000000f9 } },
+ { AR5K_RF_GAIN(57), { 0x000000f9 } },
+ { AR5K_RF_GAIN(58), { 0x000000f9 } },
+ { AR5K_RF_GAIN(59), { 0x000000f9 } },
+ { AR5K_RF_GAIN(60), { 0x000000f9 } },
+ { AR5K_RF_GAIN(61), { 0x000000f9 } },
+ { AR5K_RF_GAIN(62), { 0x000000f9 } },
+ { AR5K_RF_GAIN(63), { 0x000000f9 } },
+};
+
+/* Initial RF Gain settings for RF2425 */
+static const struct ath5k_ini_rfgain rfgain_2425[] = {
+ { AR5K_RF_GAIN(0), { 0x00000000 } },
+ { AR5K_RF_GAIN(1), { 0x00000040 } },
+ { AR5K_RF_GAIN(2), { 0x00000080 } },
+ { AR5K_RF_GAIN(3), { 0x00000181 } },
+ { AR5K_RF_GAIN(4), { 0x000001c1 } },
+ { AR5K_RF_GAIN(5), { 0x00000001 } },
+ { AR5K_RF_GAIN(6), { 0x00000041 } },
+ { AR5K_RF_GAIN(7), { 0x00000081 } },
+ { AR5K_RF_GAIN(8), { 0x00000188 } },
+ { AR5K_RF_GAIN(9), { 0x000001c8 } },
+ { AR5K_RF_GAIN(10), { 0x00000008 } },
+ { AR5K_RF_GAIN(11), { 0x00000048 } },
+ { AR5K_RF_GAIN(12), { 0x00000088 } },
+ { AR5K_RF_GAIN(13), { 0x00000189 } },
+ { AR5K_RF_GAIN(14), { 0x000001c9 } },
+ { AR5K_RF_GAIN(15), { 0x00000009 } },
+ { AR5K_RF_GAIN(16), { 0x00000049 } },
+ { AR5K_RF_GAIN(17), { 0x00000089 } },
+ { AR5K_RF_GAIN(18), { 0x000001b0 } },
+ { AR5K_RF_GAIN(19), { 0x000001f0 } },
+ { AR5K_RF_GAIN(20), { 0x00000030 } },
+ { AR5K_RF_GAIN(21), { 0x00000070 } },
+ { AR5K_RF_GAIN(22), { 0x00000171 } },
+ { AR5K_RF_GAIN(23), { 0x000001b1 } },
+ { AR5K_RF_GAIN(24), { 0x000001f1 } },
+ { AR5K_RF_GAIN(25), { 0x00000031 } },
+ { AR5K_RF_GAIN(26), { 0x00000071 } },
+ { AR5K_RF_GAIN(27), { 0x000001b8 } },
+ { AR5K_RF_GAIN(28), { 0x000001f8 } },
+ { AR5K_RF_GAIN(29), { 0x00000038 } },
+ { AR5K_RF_GAIN(30), { 0x00000078 } },
+ { AR5K_RF_GAIN(31), { 0x000000b8 } },
+ { AR5K_RF_GAIN(32), { 0x000001b9 } },
+ { AR5K_RF_GAIN(33), { 0x000001f9 } },
+ { AR5K_RF_GAIN(34), { 0x00000039 } },
+ { AR5K_RF_GAIN(35), { 0x00000079 } },
+ { AR5K_RF_GAIN(36), { 0x000000b9 } },
+ { AR5K_RF_GAIN(37), { 0x000000f9 } },
+ { AR5K_RF_GAIN(38), { 0x000000f9 } },
+ { AR5K_RF_GAIN(39), { 0x000000f9 } },
+ { AR5K_RF_GAIN(40), { 0x000000f9 } },
+ { AR5K_RF_GAIN(41), { 0x000000f9 } },
+ { AR5K_RF_GAIN(42), { 0x000000f9 } },
+ { AR5K_RF_GAIN(43), { 0x000000f9 } },
+ { AR5K_RF_GAIN(44), { 0x000000f9 } },
+ { AR5K_RF_GAIN(45), { 0x000000f9 } },
+ { AR5K_RF_GAIN(46), { 0x000000f9 } },
+ { AR5K_RF_GAIN(47), { 0x000000f9 } },
+ { AR5K_RF_GAIN(48), { 0x000000f9 } },
+ { AR5K_RF_GAIN(49), { 0x000000f9 } },
+ { AR5K_RF_GAIN(50), { 0x000000f9 } },
+ { AR5K_RF_GAIN(51), { 0x000000f9 } },
+ { AR5K_RF_GAIN(52), { 0x000000f9 } },
+ { AR5K_RF_GAIN(53), { 0x000000f9 } },
+ { AR5K_RF_GAIN(54), { 0x000000f9 } },
+ { AR5K_RF_GAIN(55), { 0x000000f9 } },
+ { AR5K_RF_GAIN(56), { 0x000000f9 } },
+ { AR5K_RF_GAIN(57), { 0x000000f9 } },
+ { AR5K_RF_GAIN(58), { 0x000000f9 } },
+ { AR5K_RF_GAIN(59), { 0x000000f9 } },
+ { AR5K_RF_GAIN(60), { 0x000000f9 } },
+ { AR5K_RF_GAIN(61), { 0x000000f9 } },
+ { AR5K_RF_GAIN(62), { 0x000000f9 } },
+ { AR5K_RF_GAIN(63), { 0x000000f9 } },
+};
+
static const struct ath5k_gain_opt rfgain_opt_5112 = {
1,
8,
entry = ((first - 1) / 8) + offset;
position = (first - 1) % 8;
- if (set == true)
+ if (set)
data = ath5k_hw_bitswap(reg, bits);
for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
last = (position + left > 8) ? 8 : position + left;
mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
- if (set == true) {
+ if (set) {
rf[entry] &= ~mask;
rf[entry] |= ((data << position) << (col * 8)) & mask;
data >>= (8 - position);
left -= 8 - position;
}
- data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
+ data = set ? 1 : ath5k_hw_bitswap(data, bits);
return data;
}
go = &rfgain_opt_5111;
break;
case AR5K_RF5112:
- case AR5K_RF5413: /* ??? */
go = &rfgain_opt_5112;
break;
default:
int obdb = -1, bank = -1;
u32 ee_mode;
- AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
+ AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
}
/* Modify bank 0 */
- if (channel->val & CHANNEL_2GHZ) {
- if (channel->val & CHANNEL_CCK)
+ if (channel->hw_value & CHANNEL_2GHZ) {
+ if (channel->hw_value & CHANNEL_CCK)
ee_mode = AR5K_EEPROM_MODE_11B;
else
ee_mode = AR5K_EEPROM_MODE_11G;
} else {
/* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
- obdb = channel->freq >= 5725 ? 3 :
- (channel->freq >= 5500 ? 2 :
- (channel->freq >= 5260 ? 1 :
- (channel->freq > 4000 ? 0 : -1)));
+ obdb = channel->center_freq >= 5725 ? 3 :
+ (channel->center_freq >= 5500 ? 2 :
+ (channel->center_freq >= 5260 ? 1 :
+ (channel->center_freq > 4000 ? 0 : -1)));
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
ee->ee_pwd_84, 1, 51, 3, true))
int obdb = -1, bank = -1;
u32 ee_mode;
- AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
+ AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
- && !test_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode)){
+ && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
rf_ini = rfregs_2112a;
rf_size = ARRAY_SIZE(rfregs_5112a);
if (mode < 2) {
}
/* Modify bank 6 */
- if (channel->val & CHANNEL_2GHZ) {
- if (channel->val & CHANNEL_OFDM)
+ if (channel->hw_value & CHANNEL_2GHZ) {
+ if (channel->hw_value & CHANNEL_OFDM)
ee_mode = AR5K_EEPROM_MODE_11G;
else
ee_mode = AR5K_EEPROM_MODE_11B;
} else {
/* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
- obdb = channel->freq >= 5725 ? 3 :
- (channel->freq >= 5500 ? 2 :
- (channel->freq >= 5260 ? 1 :
- (channel->freq > 4000 ? 0 : -1)));
+ obdb = channel->center_freq >= 5725 ? 3 :
+ (channel->center_freq >= 5500 ? 2 :
+ (channel->center_freq >= 5260 ? 1 :
+ (channel->center_freq > 4000 ? 0 : -1)));
+
+ if (obdb == -1)
+ return -EINVAL;
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
}
/*
- * Initialize RF5413/5414
+ * Initialize RF5413/5414 and future chips
+ * (until we come up with a better solution)
*/
static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
struct ieee80211_channel *channel, unsigned int mode)
unsigned int rf_size, i;
int bank = -1;
- AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
+ AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
- rf_ini = rfregs_5413;
- rf_size = ARRAY_SIZE(rfregs_5413);
+ switch (ah->ah_radio) {
+ case AR5K_RF5413:
+ rf_ini = rfregs_5413;
+ rf_size = ARRAY_SIZE(rfregs_5413);
+ break;
+ case AR5K_RF2413:
+ rf_ini = rfregs_2413;
+ rf_size = ARRAY_SIZE(rfregs_2413);
+
+ if (mode < 2) {
+ ATH5K_ERR(ah->ah_sc,
+ "invalid channel mode: %i\n", mode);
+ return -EINVAL;
+ }
+
+ mode = mode - 2;
+ break;
+ case AR5K_RF2425:
+ rf_ini = rfregs_2425;
+ rf_size = ARRAY_SIZE(rfregs_2425);
+
+ if (mode < 2) {
+ ATH5K_ERR(ah->ah_sc,
+ "invalid channel mode: %i\n", mode);
+ return -EINVAL;
+ }
+
+ /* Map b to g */
+ if (mode == 2)
+ mode = 0;
+ else
+ mode = mode - 3;
+
+ break;
+ default:
+ return -EINVAL;
+ }
/* Copy values to modify them */
for (i = 0; i < rf_size; i++) {
ah->ah_rf_banks_size = sizeof(rfregs_5413);
func = ath5k_hw_rf5413_rfregs;
break;
+ case AR5K_RF2413:
+ ah->ah_rf_banks_size = sizeof(rfregs_2413);
+ func = ath5k_hw_rf5413_rfregs;
+ break;
+ case AR5K_RF2425:
+ ah->ah_rf_banks_size = sizeof(rfregs_2425);
+ func = ath5k_hw_rf5413_rfregs;
+ break;
default:
return -EINVAL;
}
ath5k_rfg = rfgain_5413;
size = ARRAY_SIZE(rfgain_5413);
break;
+ case AR5K_RF2413:
+ ath5k_rfg = rfgain_2413;
+ size = ARRAY_SIZE(rfgain_2413);
+ freq = 0; /* only 2Ghz */
+ break;
+ case AR5K_RF2425:
+ ath5k_rfg = rfgain_2425;
+ size = ARRAY_SIZE(rfgain_2425);
+ freq = 0; /* only 2Ghz */
+ break;
default:
return -EINVAL;
}
ah->ah_gain.g_active = 1;
break;
case AR5K_RF5112:
- case AR5K_RF5413: /* ??? */
ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
ah->ah_gain.g_step =
&rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
* newer chipsets like the AR5212A who have a completely
* different RF/PHY part.
*/
- athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) |
- (1 << 6) | 0x1;
-
+ athchan = (ath5k_hw_bitswap(
+ (ieee80211_frequency_to_channel(
+ channel->center_freq) - 24) / 2, 5)
+ << 1) | (1 << 6) | 0x1;
return athchan;
}
struct ieee80211_channel *channel)
{
struct ath5k_athchan_2ghz ath5k_channel_2ghz;
- unsigned int ath5k_channel = channel->chan;
+ unsigned int ath5k_channel =
+ ieee80211_frequency_to_channel(channel->center_freq);
u32 data0, data1, clock;
int ret;
*/
data0 = data1 = 0;
- if (channel->val & CHANNEL_2GHZ) {
+ if (channel->hw_value & CHANNEL_2GHZ) {
/* Map 2GHz channel to 5GHz Atheros channel ID */
- ret = ath5k_hw_rf5111_chan2athchan(channel->chan,
- &ath5k_channel_2ghz);
+ ret = ath5k_hw_rf5111_chan2athchan(
+ ieee80211_frequency_to_channel(channel->center_freq),
+ &ath5k_channel_2ghz);
if (ret)
return ret;
u16 c;
data = data0 = data1 = data2 = 0;
- c = channel->freq;
+ c = channel->center_freq;
- /*
- * Set the channel on the RF5112 or newer
- */
if (c < 4800) {
if (!((c - 2224) % 5)) {
data0 = ((2 * (c - 704)) - 3040) / 10;
return -EINVAL;
data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
- } else {
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
if (!(c % 20) && c >= 5120) {
data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
data2 = ath5k_hw_bitswap(3, 2);
data2 = ath5k_hw_bitswap(1, 2);
} else
return -EINVAL;
+ } else {
+ data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ath5k_hw_bitswap(0, 2);
}
data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
return 0;
}
+/*
+ * Set the channel on the RF2425
+ */
+static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
+ struct ieee80211_channel *channel)
+{
+ u32 data, data0, data2;
+ u16 c;
+
+ data = data0 = data2 = 0;
+ c = channel->center_freq;
+
+ if (c < 4800) {
+ data0 = ath5k_hw_bitswap((c - 2272), 8);
+ data2 = 0;
+ /* ? 5GHz ? */
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
+ if (!(c % 20) && c < 5120)
+ data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
+ else if (!(c % 10))
+ data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
+ else if (!(c % 5))
+ data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
+ else
+ return -EINVAL;
+ data2 = ath5k_hw_bitswap(1, 2);
+ } else {
+ data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ath5k_hw_bitswap(0, 2);
+ }
+
+ data = (data0 << 4) | data2 << 2 | 0x1001;
+
+ ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
+ ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
+
+ return 0;
+}
+
/*
* Set a channel on the radio chip
*/
int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
{
int ret;
-
/*
- * Check bounds supported by the PHY
- * (don't care about regulation restrictions at this point)
- */
- if ((channel->freq < ah->ah_capabilities.cap_range.range_2ghz_min ||
- channel->freq > ah->ah_capabilities.cap_range.range_2ghz_max) &&
- (channel->freq < ah->ah_capabilities.cap_range.range_5ghz_min ||
- channel->freq > ah->ah_capabilities.cap_range.range_5ghz_max)) {
+ * Check bounds supported by the PHY (we don't care about regultory
+ * restrictions at this point). Note: hw_value already has the band
+ * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
+ * of the band by that */
+ if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
ATH5K_ERR(ah->ah_sc,
- "channel out of supported range (%u MHz)\n",
- channel->freq);
- return -EINVAL;
+ "channel frequency (%u MHz) out of supported "
+ "band range\n",
+ channel->center_freq);
+ return -EINVAL;
}
/*
case AR5K_RF5111:
ret = ath5k_hw_rf5111_channel(ah, channel);
break;
+ case AR5K_RF2425:
+ ret = ath5k_hw_rf2425_channel(ah, channel);
+ break;
default:
ret = ath5k_hw_rf5112_channel(ah, channel);
break;
if (ret)
return ret;
- ah->ah_current_channel.freq = channel->freq;
- ah->ah_current_channel.val = channel->val;
- ah->ah_turbo = channel->val == CHANNEL_T ? true : false;
+ /* Set JAPAN setting for channel 14 */
+ if (channel->center_freq == 2484) {
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
+ AR5K_PHY_CCKTXCTL_JAPAN);
+ } else {
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
+ AR5K_PHY_CCKTXCTL_WORLD);
+ }
+
+ ah->ah_current_channel.center_freq = channel->center_freq;
+ ah->ah_current_channel.hw_value = channel->hw_value;
+ ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
return 0;
}
* http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
* &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
*
+ * XXX: Since during noise floor calibration antennas are detached according to
+ * the patent, we should stop tx queues here.
*/
int
ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
s32 noise_floor;
/*
- * Enable noise floor calibration and wait until completion
+ * Enable noise floor calibration
*/
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_NF);
if (ret) {
ATH5K_ERR(ah->ah_sc,
"noise floor calibration timeout (%uMHz)\n", freq);
- return ret;
+ return -EAGAIN;
}
/* Wait until the noise floor is calibrated and read the value */
if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
ATH5K_ERR(ah->ah_sc,
"noise floor calibration failed (%uMHz)\n", freq);
- return -EIO;
+ return -EAGAIN;
}
ah->ah_noise_floor = noise_floor;
beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
- udelay(2300);
+ mdelay(2);
/*
* Set the channel (with AGC turned off)
if (ret) {
ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
- channel->freq);
+ channel->center_freq);
return ret;
}
- ret = ath5k_hw_noise_floor_calibration(ah, channel->freq);
+ ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
if (ret)
return ret;
}
/*
- * Perform a PHY calibration on RF5111/5112
+ * Perform a PHY calibration on RF5111/5112 and newer chips
*/
static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
struct ieee80211_channel *channel)
{
u32 i_pwr, q_pwr;
s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
+ int i;
ATH5K_TRACE(ah->ah_sc);
- if (ah->ah_calibration == false ||
- ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
+ if (!ah->ah_calibration ||
+ ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
goto done;
- ah->ah_calibration = false;
+ /* Calibration has finished, get the results and re-run */
+ for (i = 0; i <= 10; i++) {
+ iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
+ i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
+ q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
+ }
- iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
- i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
- q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
- q_coffd = q_pwr >> 6;
+ q_coffd = q_pwr >> 7;
+ /* No correction */
if (i_coffd == 0 || q_coffd == 0)
goto done;
i_coff = ((-iq_corr) / i_coffd) & 0x3f;
- q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
- /* Commit new IQ value */
+ /* Boundary check */
+ if (i_coff > 31)
+ i_coff = 31;
+ if (i_coff < -32)
+ i_coff = -32;
+
+ q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
+
+ /* Boundary check */
+ if (q_coff > 15)
+ q_coff = 15;
+ if (q_coff < -16)
+ q_coff = -16;
+
+ /* Commit new I/Q value */
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
+ /* Re-enable calibration -if we don't we'll commit
+ * the same values again and again */
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
+ AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
+
done:
- ath5k_hw_noise_floor_calibration(ah, channel->freq);
+
+ /* TODO: Separate noise floor calibration from I/Q calibration
+ * since noise floor calibration interrupts rx path while I/Q
+ * calibration doesn't. We don't need to run noise floor calibration
+ * as often as I/Q calibration.*/
+ ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
/* Request RF gain */
- if (channel->val & CHANNEL_5GHZ) {
+ if (channel->hw_value & CHANNEL_5GHZ) {
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
AR5K_PHY_PAPD_PROBE_TXPOWER) |
AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
return -EINVAL;
}
+ /*
+ * RF2413 for some reason can't
+ * transmit anything if we call
+ * this funtion, so we skip it
+ * until we fix txpower.
+ *
+ * XXX: Assume same for RF2425
+ * to be safe.
+ */
+ if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
+ return 0;
+
/* Reset TX power values */
memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
ah->ah_txpower.txp_tpc = tpc;
AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
- if (ah->ah_txpower.txp_tpc == true)
+ if (ah->ah_txpower.txp_tpc)
ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
else
return ath5k_hw_txpower(ah, channel, power);
}
+
+#undef _ATH5K_PHY