Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-nvram

[linux-2.6-omap-h63xx.git] / drivers / net / wireless / iwlwifi / iwl-prph.h

diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index acac629386e0cc951bbd23132033637b6dfa59b6..b7a5f23351c303c994a835124d5add570bb99ec6 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -25,7 +25,7 @@
  * in the file called LICENSE.GPL.
  *
  * Contact Information:
- * James P. Ketrenos <ipw2100-admin@linux.intel.com>
+ *  Intel Linux Wireless <ilw@linux.intel.com>
  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  *
  * BSD LICENSE
@@ -84,14 +84,16 @@
 #define APMG_CLK_VAL_DMA_CLK_RQT       (0x00000200)
 #define APMG_CLK_VAL_BSM_CLK_RQT       (0x00000800)
 
-#define APMG_PS_CTRL_VAL_RESET_REQ     (0x04000000)
 
-#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
+#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS   (0x00400000)
+#define APMG_PS_CTRL_VAL_RESET_REQ             (0x04000000)
+#define APMG_PS_CTRL_MSK_PWR_SRC               (0x03000000)
+#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN         (0x00000000)
+#define APMG_PS_CTRL_VAL_PWR_SRC_MAX           (0x01000000) /* 3945 only */
+#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX          (0x02000000)
 
-#define APMG_PS_CTRL_MSK_PWR_SRC              (0x03000000)
-#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN        (0x00000000)
-#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX         (0x01000000)
 
+#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS         (0x00000800)
 
 /**
  * BSM (Bootstrap State Machine)
@@ -156,9 +158,9 @@
  *
  * 4)  Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction
  *     images in host DRAM.  The last register loaded must be the instruction
- *     bytecount register ("1" in MSbit tells initialization uCode to load
+ *     byte count register ("1" in MSbit tells initialization uCode to load
  *     the runtime uCode):
- *     BSM_DRAM_INST_BYTECOUNT_REG = bytecount | BSM_DRAM_INST_LOAD
+ *     BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD
  *
  * 5)  Wait for "alive" notification, then issue normal runtime commands.
  *
@@ -242,7 +244,7 @@
 /**
  * Tx Scheduler
  *
- * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
+ * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
  * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
  * host DRAM.  It steers each frame's Tx command (which contains the frame
  * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
@@ -358,11 +360,6 @@
  *  7- 0:  Enable (1), disable (0), one bit for each channel 0-7
  */
 #define IWL49_SCD_TXFACT                   (IWL49_SCD_START_OFFSET + 0x1c)
-
-/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
-#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
-       ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
-
 /*
  * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
  * Initialized and updated by driver as new TFDs are added to queue.
@@ -512,11 +509,39 @@
 #define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
        ((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
 
-#define IWL49_SCD_TXFIFO_POS_TID               (0)
-#define IWL49_SCD_TXFIFO_POS_RA                        (4)
-#define IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK   (0x01FF)
+#define IWL_SCD_TXFIFO_POS_TID                 (0)
+#define IWL_SCD_TXFIFO_POS_RA                  (4)
+#define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK     (0x01FF)
 
 /* 5000 SCD */
+#define IWL50_SCD_QUEUE_STTS_REG_POS_TXF       (0)
+#define IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE    (3)
+#define IWL50_SCD_QUEUE_STTS_REG_POS_WSL       (4)
+#define IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
+#define IWL50_SCD_QUEUE_STTS_REG_MSK           (0x00FF0000)
+
+#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_POS            (8)
+#define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_MSK            (0x00FFFF00)
+#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS      (24)
+#define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK      (0xFF000000)
+#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS          (0)
+#define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK          (0x0000007F)
+#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS       (16)
+#define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK       (0x007F0000)
+
+#define IWL50_SCD_CONTEXT_DATA_OFFSET          (0x600)
+#define IWL50_SCD_TX_STTS_BITMAP_OFFSET                (0x7B1)
+#define IWL50_SCD_TRANSLATE_TBL_OFFSET         (0x7E0)
+
+#define IWL50_SCD_CONTEXT_QUEUE_OFFSET(x)\
+       (IWL50_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
+
+#define IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
+       ((IWL50_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc)
+
+#define IWL50_SCD_QUEUECHAIN_SEL_ALL(x)                (((1<<(x)) - 1) &\
+       (~(1<<IWL_CMD_QUEUE_NUM)))
+
 #define IWL50_SCD_BASE                 (PRPH_BASE + 0xa02c00)
 
 #define IWL50_SCD_SRAM_BASE_ADDR         (IWL50_SCD_BASE + 0x0)