ACPI/PCI: Set support bit for MSI in support field of _OSC

[linux-2.6-omap-h63xx.git] / drivers / pci / msi.c

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 8c61304cbb37e8b9f32343c0fb93cd73bd276d27..74801f7df9c901ad21017ce2a831e0cd61c8af1c 100644 (file)
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -70,12 +70,10 @@ arch_teardown_msi_irqs(struct pci_dev *dev)
        }
 }
 
-static void msi_set_enable(struct pci_dev *dev, int enable)
+static void __msi_set_enable(struct pci_dev *dev, int pos, int enable)
 {
-       int pos;
        u16 control;
 
-       pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
        if (pos) {
                pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
                control &= ~PCI_MSI_FLAGS_ENABLE;
@@ -85,6 +83,11 @@ static void msi_set_enable(struct pci_dev *dev, int enable)
        }
 }
 
+static void msi_set_enable(struct pci_dev *dev, int enable)
+{
+       __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable);
+}
+
 static void msix_set_enable(struct pci_dev *dev, int enable)
 {
        int pos;
@@ -123,7 +126,16 @@ static void msix_flush_writes(unsigned int irq)
        }
 }
 
-static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
+/*
+ * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
+ * mask all MSI interrupts by clearing the MSI enable bit does not work
+ * reliably as devices without an INTx disable bit will then generate a
+ * level IRQ which will never be cleared.
+ *
+ * Returns 1 if it succeeded in masking the interrupt and 0 if the device
+ * doesn't support MSI masking.
+ */
+static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
 {
        struct msi_desc *entry;
 
@@ -141,7 +153,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                        mask_bits |= flag & mask;
                        pci_write_config_dword(entry->dev, pos, mask_bits);
                } else {
-                       msi_set_enable(entry->dev, !flag);
+                       return 0;
                }
                break;
        case PCI_CAP_ID_MSIX:
@@ -157,6 +169,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                break;
        }
        entry->msi_attrib.masked = !!flag;
+       return 1;
 }
 
 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
@@ -295,9 +308,8 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
                                  entry->msi_attrib.masked);
 
        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
-       control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
-       if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
-               control |= PCI_MSI_FLAGS_ENABLE;
+       control &= ~PCI_MSI_FLAGS_QSIZE;
+       control |= PCI_MSI_FLAGS_ENABLE;
        pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 }
 
@@ -366,23 +378,21 @@ static int msi_capability_init(struct pci_dev *dev)
        entry->msi_attrib.masked = 1;
        entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
        entry->msi_attrib.pos = pos;
-       if (is_mask_bit_support(control)) {
+       if (entry->msi_attrib.maskbit) {
                entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
-                               is_64bit_address(control));
+                               entry->msi_attrib.is_64);
        }
        entry->dev = dev;
        if (entry->msi_attrib.maskbit) {
                unsigned int maskbits, temp;
                /* All MSIs are unmasked by default, Mask them all */
                pci_read_config_dword(dev,
-                       msi_mask_bits_reg(pos, is_64bit_address(control)),
+                       msi_mask_bits_reg(pos, entry->msi_attrib.is_64),
                        &maskbits);
                temp = (1 << multi_msi_capable(control));
                temp = ((temp - 1) & ~temp);
                maskbits |= temp;
-               pci_write_config_dword(dev,
-                       msi_mask_bits_reg(pos, is_64bit_address(control)),
-                       maskbits);
+               pci_write_config_dword(dev, entry->msi_attrib.is_64, maskbits);
                entry->msi_attrib.maskbits_mask = temp;
        }
        list_add_tail(&entry->list, &dev->msi_list);
@@ -561,9 +571,8 @@ int pci_enable_msi(struct pci_dev* dev)
 
        /* Check whether driver already requested for MSI-X irqs */
        if (dev->msix_enabled) {
-               printk(KERN_INFO "PCI: %s: Can't enable MSI.  "
-                       "Device already has MSI-X enabled\n",
-                       pci_name(dev));
+               dev_info(&dev->dev, "can't enable MSI "
+                        "(MSI-X already enabled)\n");
                return -EINVAL;
        }
        status = msi_capability_init(dev);
@@ -686,9 +695,8 @@ int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 
        /* Check whether driver already requested for MSI irq */
        if (dev->msi_enabled) {
-               printk(KERN_INFO "PCI: %s: Can't enable MSI-X.  "
-                      "Device already has an MSI irq assigned\n",
-                      pci_name(dev));
+               dev_info(&dev->dev, "can't enable MSI-X "
+                      "(MSI IRQ already assigned)\n");
                return -EINVAL;
        }
        status = msix_capability_init(dev, entries, nvec);
@@ -751,3 +759,24 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
 {
        INIT_LIST_HEAD(&dev->msi_list);
 }
+
+#ifdef CONFIG_ACPI
+#include <linux/acpi.h>
+#include <linux/pci-acpi.h>
+static void __devinit msi_acpi_init(void)
+{
+       if (acpi_pci_disabled)
+               return;
+       pci_osc_support_set(OSC_MSI_SUPPORT);
+       pcie_osc_support_set(OSC_MSI_SUPPORT);
+}
+#else
+static inline void msi_acpi_init(void) { }
+#endif /* CONFIG_ACPI */
+
+void __devinit msi_init(void)
+{
+       if (!pci_msi_enable)
+               return;
+       msi_acpi_init();
+}