* accesses to the SMBus registers, with potentially bad effects. Thus you
* should be very careful when adding new entries: if SMM is accessing the
* Intel SMBus, this is a very good reason to leave it hidden.
+ *
+ * Likewise, many recent laptops use ACPI for thermal management. If the
+ * ACPI DSDT code accesses the SMBus, then Linux should not access it
+ * natively, and keeping the SMBus hidden is the right thing to do. If you
+ * are about to add an entry in the table below, please first disassemble
+ * the DSDT and double-check that there is no code accessing the SMBus.
*/
static int asus_hides_smbus;
case 0x12bf: /* HP xw4100 */
asus_hides_smbus = 1;
}
- else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
- switch (dev->subsystem_device) {
- case 0x099c: /* HP Compaq nx6110 */
- asus_hides_smbus = 1;
- }
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
switch(dev->subsystem_device) {
if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
(f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
#ifdef DEBUG
- dev_dbg(&dev->dev, "calling quirk 0x%p", f->hook);
- print_fn_descriptor_symbol(": %s()\n",
+ dev_dbg(&dev->dev, "calling ");
+ print_fn_descriptor_symbol("%s()\n",
(unsigned long) f->hook);
#endif
f->hook(dev);
/* Turn off PCI Bus Parking */
pci_write_config_byte(dev, 0x76, b ^ 0x40);
+ dev_info(&dev->dev,
+ "Disabling VIA CX700 PCI parking\n");
+ }
+ }
+
+ if (pci_read_config_byte(dev, 0x72, &b) == 0) {
+ if (b != 0) {
/* Turn off PCI Master read caching */
pci_write_config_byte(dev, 0x72, 0x0);
+
+ /* Set PCI Master Bus time-out to "1x16 PCLK" */
pci_write_config_byte(dev, 0x75, 0x1);
+
+ /* Disable "Read FIFO Timer" */
pci_write_config_byte(dev, 0x77, 0x0);
- printk(KERN_INFO
- "PCI: VIA CX700 PCI parking/caching fixup on %s\n",
- pci_name(dev));
+ dev_info(&dev->dev,
+ "Disabling VIA CX700 PCI caching\n");
}
}
}
quirk_msi_ht_cap);
-/*
- * Force enable MSI mapping capability on HT bridges
- */
-static void __devinit quirk_msi_ht_cap_enable(struct pci_dev *dev)
-{
- int pos, ttl = 48;
-
- pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
- while (pos && ttl--) {
- u8 flags;
-
- if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) {
- printk(KERN_INFO "PCI: Enabling HT MSI Mapping on %s\n",
- pci_name(dev));
-
- pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
- flags | HT_MSI_FLAGS_ENABLE);
- }
- pos = pci_find_next_ht_capability(dev, pos,
- HT_CAPTYPE_MSI_MAPPING);
- }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
- PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
- quirk_msi_ht_cap_enable);
-
/* The nVidia CK804 chipset may have 2 HT MSI mappings.
* MSI are supported if the MSI capability set in any of these mappings.
*/
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
quirk_nvidia_ck804_msi_ht_cap);
-/*
- * Force enable MSI mapping capability on HT bridges */
-static inline void ht_enable_msi_mapping(struct pci_dev *dev)
+/* Force enable MSI mapping capability on HT bridges */
+static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
{
int pos, ttl = 48;
HT_CAPTYPE_MSI_MAPPING);
}
}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
+ PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
+ ht_enable_msi_mapping);
static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
{
if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
&flags) == 0) {
- dev_info(&dev->dev, "Quirk disabling HT MSI mapping");
+ dev_info(&dev->dev, "Disabling HT MSI mapping");
pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
flags & ~HT_MSI_FLAGS_ENABLE);
}