Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6

[linux-2.6-omap-h63xx.git] / drivers / pci / setup-bus.c

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 262b0439abe9e41a476629d9ac35927f2491620f..f9b7bdd278292c633717ecfe0eb265a1ed97a864 100644 (file)
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -65,6 +65,7 @@ static void pbus_assign_resources_sorted(struct pci_bus *bus)
                res = list->res;
                idx = res - &list->dev->resource[0];
                if (pci_assign_resource(list->dev, idx)) {
+                       /* FIXME: get rid of this */
                        res->start = 0;
                        res->end = 0;
                        res->flags = 0;
@@ -144,8 +145,7 @@ EXPORT_SYMBOL(pci_setup_cardbus);
    config space writes, so it's quite possible that an I/O window of
    the bridge will have some undesirable address (e.g. 0) after the
    first write. Ditto 64-bit prefetchable MMIO.  */
-static void __devinit
-pci_setup_bridge(struct pci_bus *bus)
+static void pci_setup_bridge(struct pci_bus *bus)
 {
        struct pci_dev *bridge = bus->self;
        struct pci_bus_region region;
@@ -206,10 +206,8 @@ pci_setup_bridge(struct pci_bus *bus)
        if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
                l = (region.start >> 16) & 0xfff0;
                l |= region.end & 0xfff00000;
-#ifdef CONFIG_RESOURCES_64BIT
-               bu = region.start >> 32;
-               lu = region.end >> 32;
-#endif
+               bu = upper_32_bits(region.start);
+               lu = upper_32_bits(region.end);
                DBG(KERN_INFO "  PREFETCH window: 0x%016llx-0x%016llx\n",
                    (unsigned long long)region.start,
                    (unsigned long long)region.end);
@@ -329,6 +327,7 @@ static void pbus_size_io(struct pci_bus *bus)
        /* Alignment of the IO window is always 4K */
        b_res->start = 4096;
        b_res->end = b_res->start + size - 1;
+       b_res->flags |= IORESOURCE_STARTALIGN;
 }
 
 /* Calculate the size of the bus and minimal alignment which
@@ -403,11 +402,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
        }
        b_res->start = min_align;
        b_res->end = size + min_align - 1;
+       b_res->flags |= IORESOURCE_STARTALIGN;
        return 1;
 }
 
-static void __devinit
-pci_bus_size_cardbus(struct pci_bus *bus)
+static void pci_bus_size_cardbus(struct pci_bus *bus)
 {
        struct pci_dev *bridge = bus->self;
        struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
@@ -488,12 +487,7 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus)
                break;
 
        case PCI_CLASS_BRIDGE_PCI:
-               /* don't size subtractive decoding (transparent)
-                * PCI-to-PCI bridges */
-               if (bus->self->transparent)
-                       break;
                pci_bridge_check_ranges(bus);
-               /* fall through */
        default:
                pbus_size_io(bus);
                /* If the bridge supports prefetchable range, size it