Merge master.kernel.org:/pub/scm/linux/kernel/git/herbert/crypto-2.6

[linux-2.6-omap-h63xx.git] / drivers / video / nvidia / nv_hw.c

diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
index 454283f9bdac2aafe2ca457b1f4608384a26f94c..f297c7b14a412117b2de672e68e47de9f96fb252 100644 (file)
--- a/drivers/video/nvidia/nv_hw.c
+++ b/drivers/video/nvidia/nv_hw.c
@@ -52,6 +52,7 @@
 #include <linux/pci.h>
 #include "nv_type.h"
 #include "nv_local.h"
+#include "nv_proto.h"
 
 void NVLockUnlock(struct nvidia_par *par, int Lock)
 {
@@ -144,12 +145,18 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
 
        if (par->Architecture >= NV_ARCH_40) {
                pll = NV_RD32(par->PMC, 0x4020);
-               P = (pll >> 16) & 0x03;
+               P = (pll >> 16) & 0x07;
                pll = NV_RD32(par->PMC, 0x4024);
                M = pll & 0xFF;
                N = (pll >> 8) & 0xFF;
-               MB = (pll >> 16) & 0xFF;
-               NB = (pll >> 24) & 0xFF;
+               if (((par->Chipset & 0xfff0) == 0x0290) ||
+                               ((par->Chipset & 0xfff0) == 0x0390)) {
+                       MB = 1;
+                       NB = 1;
+               } else {
+                       MB = (pll >> 16) & 0xFF;
+                       NB = (pll >> 24) & 0xFF;
+               }
                *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 
                pll = NV_RD32(par->PMC, 0x4000);
@@ -679,7 +686,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
 
        if ((par->Chipset & 0x0FF0) == 0x01A0) {
                unsigned int uMClkPostDiv;
-               dev = pci_find_slot(0, 3);
+               dev = pci_get_bus_and_slot(0, 3);
                pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
                uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
 
@@ -687,11 +694,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
                        uMClkPostDiv = 4;
                MClk = 400000 / uMClkPostDiv;
        } else {
-               dev = pci_find_slot(0, 5);
+               dev = pci_get_bus_and_slot(0, 5);
                pci_read_config_dword(dev, 0x4c, &MClk);
                MClk /= 1000;
        }
-
+       pci_dev_put(dev);
        pll = NV_RD32(par->PRAMDAC0, 0x0500);
        M = (pll >> 0) & 0xFF;
        N = (pll >> 8) & 0xFF;
@@ -700,19 +707,21 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
        sim_data.pix_bpp = (char)pixelDepth;
        sim_data.enable_video = 0;
        sim_data.enable_mp = 0;
-       pci_find_slot(0, 1);
+       dev = pci_get_bus_and_slot(0, 1);
        pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
+       pci_dev_put(dev);
        sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
        sim_data.memory_width = 64;
 
-       dev = pci_find_slot(0, 3);
+       dev = pci_get_bus_and_slot(0, 3);
        pci_read_config_dword(dev, 0, &memctrl);
+       pci_dev_put(dev);
        memctrl >>= 16;
 
        if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
                int dimm[3];
 
-               pci_find_slot(0, 2);
+               dev = pci_get_bus_and_slot(0, 2);
                pci_read_config_dword(dev, 0x40, &dimm[0]);
                dimm[0] = (dimm[0] >> 8) & 0x4f;
                pci_read_config_dword(dev, 0x44, &dimm[1]);
@@ -724,6 +733,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
                        printk("nvidiafb: your nForce DIMMs are not arranged "
                               "in optimal banks!\n");
                }
+               pci_dev_put(dev);
        }
 
        sim_data.mem_latency = 3;
@@ -885,7 +895,10 @@ void NVCalcStateExt(struct nvidia_par *par,
        case NV_ARCH_20:
        case NV_ARCH_30:
        default:
-               if (((par->Chipset & 0xffff) == 0x01A0) ||
+               if ((par->Chipset & 0xfff0) == 0x0240) {
+                       state->arbitration0 = 256;
+                       state->arbitration1 = 0x0480;
+               } else if (((par->Chipset & 0xffff) == 0x01A0) ||
                    ((par->Chipset & 0xffff) == 0x01f0)) {
                        nForceUpdateArbitrationSettings(VClk,
                                                        pixelDepth * 8,
@@ -1234,6 +1247,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
                                        break;
                                case 0x0160:
                                case 0x01D0:
+                               case 0x0240:
                                        NV_WR32(par->PMC, 0x1700,
                                                NV_RD32(par->PFB, 0x020C));
                                        NV_WR32(par->PMC, 0x1704, 0);
@@ -1358,7 +1372,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
                                                if(((par->Chipset & 0xfff0)
                                                    != 0x0160) &&
                                                   ((par->Chipset & 0xfff0)
-                                                   != 0x0220))
+                                                   != 0x0220) &&
+                                                  ((par->Chipset & 0xfff0)
+                                                   != 0x240))
                                                        NV_WR32(par->PGRAPH,
                                                                0x6900 + i*4,
                                                                NV_RD32(par->PFB,