sched: RT-balance, add new methods to sched_class

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-pxa / pxa-regs.h

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e68b593d69da28638390fa3d89b55425fc032ea9..1bd398da07da56cdee175398feebfa1eb155fcbd 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -110,7 +110,10 @@
 #define DALGN          __REG(0x400000a0)  /* DMA Alignment Register */
 #define DINT           __REG(0x400000f0)  /* DMA Interrupt Register */
 
-#define DRCMR(n)       __REG2(0x40000100, (n)<<2)
+#define DRCMR(n)       (*(((n) < 64) ? \
+                       &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
+                       &__REG2(0x40001100, ((n) & 0x3f) << 2)))
+
 #define DRCMR0         __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
 #define DRCMR1         __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
 #define DRCMR2         __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
@@ -1177,7 +1180,7 @@
 
 #define GPIO_bit(x)    (1 << ((x) & 0x1f))
 
-#ifdef CONFIG_PXA27x
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 
 /* Interrupt Controller */
 
@@ -1781,6 +1784,7 @@
 #define CCCR_M_MASK    0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
 #define CCCR_L_MASK    0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
 
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
 #define CKEN_CAMERA    (24)    /* Camera Interface Clock Enable */
 #define CKEN_SSP1      (23)    /* SSP1 Unit Clock Enable */
 #define CKEN_MEMC      (22)    /* Memory Controller Clock Enable */
@@ -1823,6 +1827,7 @@
 #define LCCR1          __REG(0x44000004)  /* LCD Controller Control Register 1 */
 #define LCCR2          __REG(0x44000008)  /* LCD Controller Control Register 2 */
 #define LCCR3          __REG(0x4400000C)  /* LCD Controller Control Register 3 */
+#define LCCR4          __REG(0x44000010)  /* LCD Controller Control Register 3 */
 #define DFBR0          __REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
 #define DFBR1          __REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
 #define LCSR           __REG(0x44000038)  /* LCD Controller Status Register */
@@ -1836,6 +1841,16 @@
 #define LCCR3_8BPP (3 << 24)
 #define LCCR3_16BPP (4 << 24)
 
+#define LCCR3_PDFOR_0 (0 << 30)
+#define LCCR3_PDFOR_1 (1 << 30)
+#define LCCR3_PDFOR_2 (2 << 30)
+#define LCCR3_PDFOR_3 (3 << 30)
+
+#define LCCR4_PAL_FOR_0 (0 << 15)
+#define LCCR4_PAL_FOR_1 (1 << 15)
+#define LCCR4_PAL_FOR_2 (2 << 15)
+#define LCCR4_PAL_FOR_MASK (3 << 15)
+
 #define FDADR0         __REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
 #define FSADR0         __REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
 #define FIDR0          __REG(0x44000208)  /* DMA Channel 0 Frame ID Register */