Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-pxa / pxa-regs.h

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 442494d71f12d38ff4dfefb8b5e9246447b73201..2357a73340d4200c39743268fe930826d341a601 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -520,6 +520,9 @@
 #define MCCR_FSRIE     (1 << 1)        /* FIFO Service Request Interrupt Enable */
 
 #define GCR            __REG(0x4050000C)  /* Global Control Register */
+#ifdef CONFIG_PXA3xx
+#define GCR_CLKBPB     (1 << 31)       /* Internal clock enable */
+#endif
 #define GCR_nDMAEN     (1 << 24)       /* non DMA Enable */
 #define GCR_CDONE_IE   (1 << 19)       /* Command Done Interrupt Enable */
 #define GCR_SDONE_IE   (1 << 18)       /* Status Done Interrupt Enable */
@@ -737,25 +740,25 @@
 
 #define USIR0          __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
 
-#define USIR0_IR0      (1 << 0)        /* Interrup request ep 0 */
-#define USIR0_IR1      (1 << 1)        /* Interrup request ep 1 */
-#define USIR0_IR2      (1 << 2)        /* Interrup request ep 2 */
-#define USIR0_IR3      (1 << 3)        /* Interrup request ep 3 */
-#define USIR0_IR4      (1 << 4)        /* Interrup request ep 4 */
-#define USIR0_IR5      (1 << 5)        /* Interrup request ep 5 */
-#define USIR0_IR6      (1 << 6)        /* Interrup request ep 6 */
-#define USIR0_IR7      (1 << 7)        /* Interrup request ep 7 */
+#define USIR0_IR0      (1 << 0)        /* Interrupt request ep 0 */
+#define USIR0_IR1      (1 << 1)        /* Interrupt request ep 1 */
+#define USIR0_IR2      (1 << 2)        /* Interrupt request ep 2 */
+#define USIR0_IR3      (1 << 3)        /* Interrupt request ep 3 */
+#define USIR0_IR4      (1 << 4)        /* Interrupt request ep 4 */
+#define USIR0_IR5      (1 << 5)        /* Interrupt request ep 5 */
+#define USIR0_IR6      (1 << 6)        /* Interrupt request ep 6 */
+#define USIR0_IR7      (1 << 7)        /* Interrupt request ep 7 */
 
 #define USIR1          __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
 
-#define USIR1_IR8      (1 << 0)        /* Interrup request ep 8 */
-#define USIR1_IR9      (1 << 1)        /* Interrup request ep 9 */
-#define USIR1_IR10     (1 << 2)        /* Interrup request ep 10 */
-#define USIR1_IR11     (1 << 3)        /* Interrup request ep 11 */
-#define USIR1_IR12     (1 << 4)        /* Interrup request ep 12 */
-#define USIR1_IR13     (1 << 5)        /* Interrup request ep 13 */
-#define USIR1_IR14     (1 << 6)        /* Interrup request ep 14 */
-#define USIR1_IR15     (1 << 7)        /* Interrup request ep 15 */
+#define USIR1_IR8      (1 << 0)        /* Interrupt request ep 8 */
+#define USIR1_IR9      (1 << 1)        /* Interrupt request ep 9 */
+#define USIR1_IR10     (1 << 2)        /* Interrupt request ep 10 */
+#define USIR1_IR11     (1 << 3)        /* Interrupt request ep 11 */
+#define USIR1_IR12     (1 << 4)        /* Interrupt request ep 12 */
+#define USIR1_IR13     (1 << 5)        /* Interrupt request ep 13 */
+#define USIR1_IR14     (1 << 6)        /* Interrupt request ep 14 */
+#define USIR1_IR15     (1 << 7)        /* Interrupt request ep 15 */
 
 #elif defined(CONFIG_PXA27x)
 
@@ -1020,7 +1023,7 @@
 #define ICSR0          __REG(0x40800014)  /* ICP Status Register 0 */
 #define ICSR1          __REG(0x40800018)  /* ICP Status Register 1 */
 
-#define ICCR0_AME      (1 << 7)        /* Adress match enable */
+#define ICCR0_AME      (1 << 7)        /* Address match enable */
 #define ICCR0_TIE      (1 << 6)        /* Transmit FIFO interrupt enable */
 #define ICCR0_RIE      (1 << 5)        /* Recieve FIFO interrupt enable */
 #define ICCR0_RXE      (1 << 4)        /* Receive enable */
@@ -1131,6 +1134,19 @@
  * General Purpose I/O
  */
 
+#define GPIO0_BASE     ((void __iomem *)io_p2v(0x40E00000))
+#define GPIO1_BASE     ((void __iomem *)io_p2v(0x40E00004))
+#define GPIO2_BASE     ((void __iomem *)io_p2v(0x40E00008))
+#define GPIO3_BASE     ((void __iomem *)io_p2v(0x40E00100))
+
+#define GPLR_OFFSET    0x00
+#define GPDR_OFFSET    0x0C
+#define GPSR_OFFSET    0x18
+#define GPCR_OFFSET    0x24
+#define GRER_OFFSET    0x30
+#define GFER_OFFSET    0x3C
+#define GEDR_OFFSET    0x48
+
 #define GPLR0          __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
 #define GPLR1          __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
 #define GPLR2          __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */