Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-pxa / pxa-regs.h

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a75a2470f4f59a1e2f23bc5d9e8a5b7707b016f9..c8f53a71c076b84210ab54320979aa955e623c9c 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -108,6 +108,7 @@
 #define DCSR_STARTINTR (1 << 1)        /* Start Interrupt (read / write) */
 #define DCSR_BUSERR    (1 << 0)        /* Bus Error Interrupt (read / write) */
 
+#define DALGN          __REG(0x400000a0)  /* DMA Alignment Register */
 #define DINT           __REG(0x400000f0)  /* DMA Interrupt Register */
 
 #define DRCMR(n)       __REG2(0x40000100, (n)<<2)
@@ -484,7 +485,7 @@
 #define SACR1_ENLBF    (1 << 5)        /* Enable Loopback */
 #define SACR1_DRPL     (1 << 4)        /* Disable Replaying Function */
 #define SACR1_DREC     (1 << 3)        /* Disable Recording Function */
-#define SACR1_AMSL     (1 << 1)        /* Specify Alternate Mode */
+#define SACR1_AMSL     (1 << 0)        /* Specify Alternate Mode */
 
 #define SASR0_I2SOFF   (1 << 7)        /* Controller Status */
 #define SASR0_ROR      (1 << 6)        /* Rx FIFO Overrun */
@@ -1614,8 +1615,21 @@
 #define SSCR0_National (0x2 << 4)      /* National Microwire */
 #define SSCR0_ECS      (1 << 6)        /* External clock select */
 #define SSCR0_SSE      (1 << 7)        /* Synchronous Serial Port Enable */
+#if defined(CONFIG_PXA25x)
 #define SSCR0_SCR      (0x0000ff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x)
+#define SSCR0_SCR      (0x000fff00)    /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#define SSCR0_EDSS     (1 << 20)       /* Extended data size select */
+#define SSCR0_NCS      (1 << 21)       /* Network clock select */
+#define SSCR0_RIM      (1 << 22)       /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM      (1 << 23)       /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC     (0x07000000)    /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(c) ((x) - 1) /* Time slots per frame [1..8] */
+#define SSCR0_ADC      (1 << 30)       /* Audio clock select */
+#define SSCR0_MOD      (1 << 31)       /* Mode (normal or network) */
+#endif
 
 #define SSCR1_RIE      (1 << 0)        /* Receive FIFO Interrupt Enable */
 #define SSCR1_TIE      (1 << 1)        /* Transmit FIFO Interrupt Enable */
@@ -2042,6 +2056,18 @@
 
 #ifdef CONFIG_PXA27x
 
+#define ARB_CNTRL      __REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK       (1<<31)    /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK            (1<<30)    /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK        (1<<29)    /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK       (1<<28)    /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK           (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK           (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK           (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK          (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG          (1<<23)    /* Only Locking masters gain access to the bus */
+
 /*
  * Keypad
  */