[ARM] 4299/1: S3C AC97 fill in register bit defines

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-s3c2410 / regs-mem.h

diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index 1a1328ac0d79bdc9c0fea701657d78d70f163394..e4d82341f7badd15ff6fddc18c2824e0993f01da 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -8,11 +8,6 @@
  * published by the Free Software Foundation.
  *
  * S3C2410 Memory Control register definitions
- *
- *  Changelog:
- *     29-Sep-2004  BJD  Initial include for Linux
- *      10-Mar-2005  LCVR Changed S3C2410_VA to S3C24XX_VA
- *
 */
 
 #ifndef __ASM_ARM_MEMREGS_H
@@ -138,10 +133,10 @@
 #define S3C2410_BANKCON_SDRAM          (0x3 << 15)
 
 /* next bits only for EDO DRAM in 6,7 */
-#define S3C2400_BANKCON_EDO_Trdc1      (0x00 << 4)
-#define S3C2400_BANKCON_EDO_Trdc2      (0x01 << 4)
-#define S3C2400_BANKCON_EDO_Trdc3      (0x02 << 4)
-#define S3C2400_BANKCON_EDO_Trdc4      (0x03 << 4)
+#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
 
 /* CAS pulse width */
 #define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
@@ -158,9 +153,9 @@
 #define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
 
 /* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trdc2          (0x00 << 2)
-#define S3C2410_BANKCON_Trdc3          (0x01 << 2)
-#define S3C2410_BANKCON_Trdc4          (0x02 << 2)
+#define S3C2410_BANKCON_Trcd2          (0x00 << 2)
+#define S3C2410_BANKCON_Trcd3          (0x01 << 2)
+#define S3C2410_BANKCON_Trcd4          (0x02 << 2)
 
 /* control column address select */
 #define S3C2410_BANKCON_SCANb8         (0x00 << 0)
@@ -183,6 +178,12 @@
 #define S3C2410_REFRESH_TRP_3clk       (1<<20)
 #define S3C2410_REFRESH_TRP_4clk       (2<<20)
 
+#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
+#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
+#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
+#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
+#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
+
 #define S3C2410_REFRESH_TSRC_MASK      (3<<18)
 #define S3C2410_REFRESH_TSRC_4clk      (0<<18)
 #define S3C2410_REFRESH_TSRC_5clk      (1<<18)
@@ -205,6 +206,7 @@
 #define S3C2410_BANKSIZE_4M            (0x5 << 0)
 #define S3C2410_BANKSIZE_2M            (0x4 << 0)
 #define S3C2410_BANKSIZE_MASK          (0x7 << 0)
+#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
 #define S3C2410_BANKSIZE_SCLK_EN       (1<<4)
 #define S3C2410_BANKSIZE_SCKE_EN       (1<<5)
 #define S3C2410_BANKSIZE_BURST         (1<<7)