Merge git://git.infradead.org/mtd-2.6

[linux-2.6-omap-h63xx.git] / include / asm-arm / spinlock.h

diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index cb4906b4555583d36c0b3b91f94d2d9d9a4724c4..800ba5254dafef9bff57c98a19dcb599b0982cbc 100644 (file)
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -30,6 +30,9 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
        __asm__ __volatile__(
 "1:    ldrex   %0, [%1]\n"
 "      teq     %0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"      wfene\n"
+#endif
 "      strexeq %0, %2, [%1]\n"
 "      teqeq   %0, #0\n"
 "      bne     1b"
@@ -65,7 +68,11 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
        smp_mb();
 
        __asm__ __volatile__(
-"      str     %1, [%0]"
+"      str     %1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"      mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
+"      sev"
+#endif
        :
        : "r" (&lock->lock), "r" (0)
        : "cc");
@@ -78,15 +85,17 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  * Write locks are easy - we just set bit 31.  When unlocking, we can
  * just write zero since the lock is exclusively held.
  */
-#define rwlock_is_locked(x)    (*((volatile unsigned int *)(x)) != 0)
 
-static inline void __raw_write_lock(rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
 
        __asm__ __volatile__(
 "1:    ldrex   %0, [%1]\n"
 "      teq     %0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"      wfene\n"
+#endif
 "      strexeq %0, %2, [%1]\n"
 "      teq     %0, #0\n"
 "      bne     1b"
@@ -97,7 +106,7 @@ static inline void __raw_write_lock(rwlock_t *rw)
        smp_mb();
 }
 
-static inline int __raw_write_trylock(rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
 
@@ -122,12 +131,19 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
        smp_mb();
 
        __asm__ __volatile__(
-       "str    %1, [%0]"
+       "str    %1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"      mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
+"      sev\n"
+#endif
        :
        : "r" (&rw->lock), "r" (0)
        : "cc");
 }
 
+/* write_can_lock - would write_trylock() succeed? */
+#define __raw_write_can_lock(x)                ((x)->lock == 0x80000000)
+
 /*
  * Read locks are a bit more hairy:
  *  - Exclusively load the lock value.
@@ -148,6 +164,9 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
 "1:    ldrex   %0, [%2]\n"
 "      adds    %0, %0, #1\n"
 "      strexpl %1, %0, [%2]\n"
+#ifdef CONFIG_CPU_32v6K
+"      wfemi\n"
+#endif
 "      rsbpls  %0, %1, #0\n"
 "      bmi     1b"
        : "=&r" (tmp), "=&r" (tmp2)
@@ -157,7 +176,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
        smp_mb();
 }
 
-static inline void __raw_read_unlock(rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
        unsigned long tmp, tmp2;
 
@@ -169,11 +188,37 @@ static inline void __raw_read_unlock(rwlock_t *rw)
 "      strex   %1, %0, [%2]\n"
 "      teq     %1, #0\n"
 "      bne     1b"
+#ifdef CONFIG_CPU_32v6K
+"\n    cmp     %0, #0\n"
+"      mcreq   p15, 0, %0, c7, c10, 4\n"
+"      seveq"
+#endif
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&rw->lock)
        : "cc");
 }
 
-#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+       unsigned long tmp, tmp2 = 1;
+
+       __asm__ __volatile__(
+"1:    ldrex   %0, [%2]\n"
+"      adds    %0, %0, #1\n"
+"      strexpl %1, %0, [%2]\n"
+       : "=&r" (tmp), "+r" (tmp2)
+       : "r" (&rw->lock)
+       : "cc");
+
+       smp_mb();
+       return tmp2 == 0;
+}
+
+/* read_can_lock - would read_trylock() succeed? */
+#define __raw_read_can_lock(x)         ((x)->lock < 0x80000000)
+
+#define _raw_spin_relax(lock)  cpu_relax()
+#define _raw_read_relax(lock)  cpu_relax()
+#define _raw_write_relax(lock) cpu_relax()
 
 #endif /* __ASM_SPINLOCK_H */