hwmon: (lm85) Don't write back cached values

[linux-2.6-omap-h63xx.git] / include / asm-mips / cpu-info.h

diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360bb5712e9c5b4607ae7d1e1152d66..2de73dbb2e9e3cac04f2ad7c7abf0654acbbf0bb 100644 (file)
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,7 +54,9 @@ struct cpuinfo_mips {
        struct cache_desc       dcache; /* Primary D or combined I/D cache */
        struct cache_desc       scache; /* Secondary cache */
        struct cache_desc       tcache; /* Tertiary/split secondary cache */
-#if defined(CONFIG_MIPS_MT_SMTC)
+       int                     srsets; /* Shadow register sets */
+       int                     core;   /* physical core number */
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
        /*
         * In the MIPS MT "SMTC" model, each TC is considered
         * to be a "CPU" for the purposes of scheduling, but
@@ -62,8 +64,10 @@ struct cpuinfo_mips {
         * to all TCs within the same VPE.
         */
        int                     vpe_id;  /* Virtual Processor number */
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
        int                     tc_id;   /* Thread Context number */
-#endif /* CONFIG_MIPS_MT */
+#endif
        void                    *data;  /* Additional data */
 } __attribute__((aligned(SMP_CACHE_BYTES)));