]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - include/asm-mips/interrupt.h
[PATCH] autofs4: add v5 follow_link mount trigger method
[linux-2.6-omap-h63xx.git] / include / asm-mips / interrupt.h
index a5735761f5e58054498b32a03bed21df06339470..774348734fa0b38a8fbe916972a966a59302be17 100644 (file)
@@ -47,6 +47,17 @@ static inline void local_irq_enable(void)
  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
  * no nops at all.
  */
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
 __asm__ (
        "       .macro  local_irq_disable\n"
        "       .set    push                                            \n"
@@ -55,8 +66,8 @@ __asm__ (
        "       di                                                      \n"
 #else
        "       mfc0    $1,$12                                          \n"
-       "       ori     $1,1                                            \n"
-       "       xori    $1,1                                            \n"
+       "       ori     $1,0x1f                                         \n"
+       "       xori    $1,0x1f                                         \n"
        "       .set    noreorder                                       \n"
        "       mtc0    $1,$12                                          \n"
 #endif
@@ -93,10 +104,11 @@ __asm__ (
        "       .set    noat                                            \n"
 #ifdef CONFIG_CPU_MIPSR2
        "       di      \\result                                        \n"
+       "       andi    \\result, 1                                     \n"
 #else
        "       mfc0    \\result, $12                                   \n"
-       "       ori     $1, \\result, 1                                 \n"
-       "       xori    $1, 1                                           \n"
+       "       ori     $1, \\result, 0x1f                              \n"
+       "       xori    $1, 0x1f                                        \n"
        "       .set    noreorder                                       \n"
        "       mtc0    $1, $12                                         \n"
 #endif
@@ -113,6 +125,7 @@ __asm__ __volatile__(                                                       \
 
 __asm__ (
        "       .macro  local_irq_restore flags                         \n"
+       "       .set    push                                            \n"
        "       .set    noreorder                                       \n"
        "       .set    noat                                            \n"
 #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
@@ -134,14 +147,13 @@ __asm__ (
 #else
        "       mfc0    $1, $12                                         \n"
        "       andi    \\flags, 1                                      \n"
-       "       ori     $1, 1                                           \n"
-       "       xori    $1, 1                                           \n"
+       "       ori     $1, 0x1f                                        \n"
+       "       xori    $1, 0x1f                                        \n"
        "       or      \\flags, $1                                     \n"
        "       mtc0    \\flags, $12                                    \n"
 #endif
        "       irq_disable_hazard                                      \n"
-       "       .set    at                                              \n"
-       "       .set    reorder                                         \n"
+       "       .set    pop                                             \n"
        "       .endm                                                   \n");
 
 #define local_irq_restore(flags)                                       \