x86: PAT export resource_wc in pci sysfs

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / immap_qe.h

diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index aba9806b31c9f7faa879cb4547821b48bf15289f..7b6f411db3e680c17cf6c819268ba73988f7399e 100644 (file)
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -20,6 +20,7 @@
 #ifdef __KERNEL__
 
 #include <linux/kernel.h>
+#include <asm/io.h>
 
 #define QE_IMMAP_SIZE  (1024 * 1024)   /* 1MB from 1MB+IMMR */
 
@@ -393,9 +394,39 @@ struct dbg {
        u8      res2[0x48];
 } __attribute__ ((packed));
 
-/* RISC Special Registers (Trap and Breakpoint) */
+/*
+ * RISC Special Registers (Trap and Breakpoint).  These are described in
+ * the QE Developer's Handbook.
+ */
 struct rsp {
-       u32     reg[0x40];      /* 64 32-bit registers */
+       __be32 tibcr[16];       /* Trap/instruction breakpoint control regs */
+       u8 res0[64];
+       __be32 ibcr0;
+       __be32 ibs0;
+       __be32 ibcnr0;
+       u8 res1[4];
+       __be32 ibcr1;
+       __be32 ibs1;
+       __be32 ibcnr1;
+       __be32 npcr;
+       __be32 dbcr;
+       __be32 dbar;
+       __be32 dbamr;
+       __be32 dbsr;
+       __be32 dbcnr;
+       u8 res2[12];
+       __be32 dbdr_h;
+       __be32 dbdr_l;
+       __be32 dbdmr_h;
+       __be32 dbdmr_l;
+       __be32 bsr;
+       __be32 bor;
+       __be32 bior;
+       u8 res3[4];
+       __be32 iatr[4];
+       __be32 eccr;            /* Exception control configuration register */
+       __be32 eicr;
+       u8 res4[0x100-0xf8];
 } __attribute__ ((packed));
 
 struct qe_immap {
@@ -438,7 +469,7 @@ struct qe_immap {
        u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
 } __attribute__ ((packed));
 
-extern struct qe_immap *qe_immr;
+extern struct qe_immap __iomem *qe_immr;
 extern phys_addr_t get_qe_base(void);
 
 static inline unsigned long immrbar_virt_to_phys(void *address)