module: Enhance verify_export_symbols

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / mpic.h

diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index b71e7b32a5550abb26b7ddfeedca5e6503f6e1da..943c5a3fac8aefa3a8e412b77a223957f01c0e6b 100644 (file)
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include <linux/irq.h>
+#include <linux/sysdev.h>
 #include <asm/dcr.h>
 
 /*
@@ -21,7 +22,9 @@
 #define MPIC_GREG_GLOBAL_CONF_0                0x00020
 #define                MPIC_GREG_GCONF_RESET                   0x80000000
 #define                MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
+#define                MPIC_GREG_GCONF_NO_BIAS                 0x10000000
 #define                MPIC_GREG_GCONF_BASE_MASK               0x000fffff
+#define                MPIC_GREG_GCONF_MCK                     0x08000000
 #define MPIC_GREG_GLOBAL_CONF_1                0x00030
 #define                MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
 #define                MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
@@ -77,6 +80,7 @@
 #define        MPIC_CPU_WHOAMI_MASK                    0x0000001f
 #define MPIC_CPU_INTACK                        0x000a0
 #define MPIC_CPU_EOI                   0x000b0
+#define MPIC_CPU_MCACK                 0x000c0
 
 /*
  * Per-source registers
@@ -102,21 +106,6 @@
 #define MPIC_MAX_CPUS          32
 #define MPIC_MAX_ISU           32
 
-/*
- * Special vector numbers (internal use only)
- */
-#define MPIC_VEC_SPURRIOUS     255
-#define MPIC_VEC_IPI_3         254
-#define MPIC_VEC_IPI_2         253
-#define MPIC_VEC_IPI_1         252
-#define MPIC_VEC_IPI_0         251
-
-/* unused */
-#define MPIC_VEC_TIMER_3       250
-#define MPIC_VEC_TIMER_2       249
-#define MPIC_VEC_TIMER_1       248
-#define MPIC_VEC_TIMER_0       247
-
 /*
  * Tsi108 implementation of MPIC has many differences from the original one
  */
@@ -155,6 +144,7 @@
 #define TSI108_CPU_WHOAMI              0xffffffff
 #define TSI108_CPU_INTACK              0x00004
 #define TSI108_CPU_EOI                 0x00008
+#define TSI108_CPU_MCACK               0x00004 /* Doesn't really exist here */
 
 /*
  * Per-source registers
@@ -197,6 +187,7 @@ enum {
        MPIC_IDX_CPU_WHOAMI,
        MPIC_IDX_CPU_INTACK,
        MPIC_IDX_CPU_EOI,
+       MPIC_IDX_CPU_MCACK,
 
        MPIC_IDX_IRQ_BASE,
        MPIC_IDX_IRQ_STRIDE,
@@ -214,7 +205,7 @@ enum {
 };
 
 
-#ifdef CONFIG_MPIC_BROKEN_U3
+#ifdef CONFIG_MPIC_U3_HT_IRQS
 /* Fixup table entry */
 struct mpic_irq_fixup
 {
@@ -223,7 +214,7 @@ struct mpic_irq_fixup
        u32             data;
        unsigned int    index;
 };
-#endif /* CONFIG_MPIC_BROKEN_U3 */
+#endif /* CONFIG_MPIC_U3_HT_IRQS */
 
 
 enum mpic_reg_type {
@@ -238,23 +229,26 @@ struct mpic_reg_bank {
        u32 __iomem     *base;
 #ifdef CONFIG_PPC_DCR
        dcr_host_t      dhost;
-       unsigned int    dbase;
-       unsigned int    doff;
 #endif /* CONFIG_PPC_DCR */
 };
 
+struct mpic_irq_save {
+       u32             vecprio,
+                       dest;
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+       u32             fixup_data;
+#endif
+};
+
 /* The instance data of a given MPIC */
 struct mpic
 {
-       /* The device node of the interrupt controller */
-       struct device_node      *of_node;
-
        /* The remapper for this MPIC */
        struct irq_host         *irqhost;
 
        /* The "linux" controller struct */
        struct irq_chip         hc_irq;
-#ifdef CONFIG_MPIC_BROKEN_U3
+#ifdef CONFIG_MPIC_U3_HT_IRQS
        struct irq_chip         hc_ht_irq;
 #endif
 #ifdef CONFIG_SMP
@@ -276,7 +270,14 @@ struct mpic
        unsigned char           *senses;
        unsigned int            senses_count;
 
-#ifdef CONFIG_MPIC_BROKEN_U3
+       /* vector numbers used for internal sources (ipi/timers) */
+       unsigned int            ipi_vecs[4];
+       unsigned int            timer_vecs[4];
+
+       /* Spurious vector to program into unused sources */
+       unsigned int            spurious_vec;
+
+#ifdef CONFIG_MPIC_U3_HT_IRQS
        /* The fixup table */
        struct mpic_irq_fixup   *fixups;
        spinlock_t              fixup_lock;
@@ -291,17 +292,31 @@ struct mpic
        struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
        struct mpic_reg_bank    isus[MPIC_MAX_ISU];
 
-#ifdef CONFIG_PPC_DCR
-       unsigned int            dcr_base;
-#endif
+       /* Protected sources */
+       unsigned long           *protected;
 
 #ifdef CONFIG_MPIC_WEIRD
        /* Pointer to HW info array */
        u32                     *hw_set;
 #endif
 
+#ifdef CONFIG_PCI_MSI
+       spinlock_t              bitmap_lock;
+       unsigned long           *hwirq_bitmap;
+#endif
+
+#ifdef CONFIG_MPIC_BROKEN_REGREAD
+       u32                     isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
+#endif
+
        /* link */
        struct mpic             *next;
+
+       struct sys_device       sysdev;
+
+#ifdef CONFIG_PM
+       struct mpic_irq_save    *save_data;
+#endif
 };
 
 /*
@@ -321,7 +336,7 @@ struct mpic
 /* Set this for a big-endian MPIC */
 #define MPIC_BIG_ENDIAN                        0x00000002
 /* Broken U3 MPIC */
-#define MPIC_BROKEN_U3                 0x00000004
+#define MPIC_U3_HT_IRQS                        0x00000004
 /* Broken IPI registers (autodetected) */
 #define MPIC_BROKEN_IPI                        0x00000008
 /* MPIC wants a reset */
@@ -332,6 +347,12 @@ struct mpic
 #define MPIC_NO_PTHROU_DIS             0x00000040
 /* DCR based MPIC */
 #define MPIC_USES_DCR                  0x00000080
+/* MPIC has 11-bit vector fields (or larger) */
+#define MPIC_LARGE_VECTORS             0x00000100
+/* Enable delivery of prio 15 interrupts as MCK instead of EE */
+#define MPIC_ENABLE_MCK                        0x00000200
+/* Disable bias among target selection, spread interrupts evenly */
+#define MPIC_NO_BIAS                   0x00000400
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK               0xf0000000
@@ -358,7 +379,7 @@ struct mpic
  * @senses_num: number of entries in the array
  *
  * Note about the sense array. If none is passed, all interrupts are
- * setup to be level negative unless MPIC_BROKEN_U3 is set in which
+ * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
  * case they are edge positive (and the array is ignored anyway).
  * The values in the array start at the first source of the MPIC,
  * that is senses[0] correspond to linux irq "irq_offset".
@@ -435,10 +456,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 void smp_mpic_message_pass(int target, int msg);
 
+/* Unmask a specific virq */
+extern void mpic_unmask_irq(unsigned int irq);
+/* Mask a specific virq */
+extern void mpic_mask_irq(unsigned int irq);
+/* EOI a specific virq */
+extern void mpic_end_irq(unsigned int irq);
+
 /* Fetch interrupt from a given mpic */
 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
-/* This one gets to the primary mpic */
+/* This one gets from the primary mpic */
 extern unsigned int mpic_get_irq(void);
+/* Fetch Machine Check interrupt from primary mpic */
+extern unsigned int mpic_get_mcirq(void);
 
 /* Set the EPIC clock ratio */
 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);