[PATCH] powerpc: Export htab start/end via device tree

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / reg.h

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 06a1f0f2db21708e688e187569064e2041fd87ad..eb392d038ed7dacdaea492f65f6311494bed17cd 100644 (file)
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -16,7 +16,11 @@
 /* Pickup Book E specific registers. */
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include <asm/reg_booke.h>
-#endif
+#endif /* CONFIG_BOOKE || CONFIG_40x */
+
+#ifdef CONFIG_8xx
+#include <asm/reg_8xx.h>
+#endif /* CONFIG_8xx */
 
 #define MSR_SF_LG      63              /* Enable 64 bit mode */
 #define MSR_ISF_LG     61              /* Interrupt 64b mode valid on 630 */
@@ -51,9 +55,17 @@
 #define __MASK(X)      (1UL<<(X))
 #endif
 
+#ifdef CONFIG_PPC64
 #define MSR_SF         __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
 #define MSR_ISF                __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
 #define MSR_HV                 __MASK(MSR_HV_LG)       /* Hypervisor state */
+#else
+/* so tests for these bits fail on 32-bit */
+#define MSR_SF         0
+#define MSR_ISF                0
+#define MSR_HV         0
+#endif
+
 #define MSR_VEC                __MASK(MSR_VEC_LG)      /* Enable AltiVec */
 #define MSR_POW                __MASK(MSR_POW_LG)      /* Enable Power Management */
 #define MSR_WE         __MASK(MSR_WE_LG)       /* Wait State Enable */
@@ -351,6 +363,7 @@
 #define SPRN_RPA       0x3D6   /* Required Physical Address Register */
 #define SPRN_SDA       0x3BF   /* Sampled Data Address Register */
 #define SPRN_SDR1      0x019   /* MMU Hash Base Register */
+#define SPRN_ASR       0x118   /* Address Space Register */
 #define SPRN_SIA       0x3BB   /* Sampled Instruction Address Register */
 #define SPRN_SPRG0     0x110   /* Special Purpose Register General 0 */
 #define SPRN_SPRG1     0x111   /* Special Purpose Register General 1 */
@@ -388,6 +401,9 @@
 #define SPRN_VRSAVE    0x100   /* Vector Register Save Register */
 #define SPRN_XER       0x001   /* Fixed Point Exception Register */
 
+#define SPRN_SCOMC     0x114   /* SCOM Access Control */
+#define SPRN_SCOMD     0x115   /* SCOM Access DATA */
+
 /* Performance monitor SPRs */
 #ifdef CONFIG_PPC64
 #define SPRN_MMCR0     795
@@ -538,6 +554,7 @@
 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
                                     : : "r" (v))
 #define mtmsrd(v)      __mtmsrd((v), 0)
+#define mtmsr(v)       mtmsrd(v)
 #else
 #define mtmsr(v)       asm volatile("mtmsr %0" : : "r" (v))
 #endif
@@ -586,13 +603,10 @@ static inline void ppc64_runlatch_off(void)
        }
 }
 
-static inline void set_tb(unsigned int upper, unsigned int lower)
-{
-       mttbl(0);
-       mttbu(upper);
-       mttbl(lower);
-}
-#endif
+extern unsigned long scom970_read(unsigned int address);
+extern void scom970_write(unsigned int address, unsigned long value);
+
+#endif /* CONFIG_PPC64 */
 
 #define __get_SP()     ({unsigned long sp; \
                        asm volatile("mr %0,1": "=r" (sp)); sp;})