struct spu_context;
struct spu_runqueue;
+struct device_node;
struct spu {
const char *name;
struct spu_runqueue *rq;
unsigned long long timestamp;
pid_t pid;
- int prio;
int class_0_pending;
spinlock_t register_lock;
char irq_c1[8];
char irq_c2[8];
+ u64 spe_id;
+
void* pdata; /* platform private data */
+
+ /* of based platforms only */
+ struct device_node *devnode;
+
+ /* native only */
+ struct spu_priv1 __iomem *priv1;
+
+ /* beat only */
+ u64 shadow_int_mask_RW[3];
+
struct sys_device sysdev;
+
+ struct {
+ /* protected by interrupt reentrancy */
+ unsigned long long slb_flt;
+ unsigned long long class2_intr;
+ } stats;
};
struct spu *spu_alloc(void);
int spu_irq_class_1_bottom(struct spu *spu);
void spu_irq_setaffinity(struct spu *spu, int cpu);
+extern void spu_invalidate_slbs(struct spu *spu);
+extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
+
+/* Calls from the memory management to the SPU */
+struct mm_struct;
+extern void spu_flush_all_slbs(struct mm_struct *mm);
+
/* system callbacks from the SPU */
struct spu_syscall_block {
u64 nr_ret;
#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
#define MFC_STATE1_RELOCATE_MASK 0x10ull
#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
+#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
u64 mfc_lpid_RW; /* 0x008 */
u64 spu_idr_RW; /* 0x010 */
u64 mfc_vr_RO; /* 0x018 */