[PATCH] powerpc: IOMMU support for honoring dma_mask

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / spu.h

diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 698c4cb08c6024b2694c2f694191fa0695f4ab78..f431d8b0b6514bd5649b407ba1078aae5f477dfd 100644 (file)
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -22,13 +22,13 @@
 
 #ifndef _SPU_H
 #define _SPU_H
+#ifdef __KERNEL__
+
 #include <linux/config.h>
 #include <linux/kref.h>
 #include <linux/workqueue.h>
 
-#define LS_ORDER (6)           /* 256 kb */
-
-#define LS_SIZE (PAGE_SIZE << LS_ORDER)
+#define LS_SIZE (256 * 1024)
 #define LS_ADDR_MASK (LS_SIZE - 1)
 
 #define MFC_PUT_CMD             0x20
@@ -100,10 +100,8 @@
 #define MFC_MULTI_SRC_EVENT                 0x00001000
 
 /* Flags indicating progress during context switch. */
-#define SPU_CONTEXT_SWITCH_PENDING_nr  0UL
-#define SPU_CONTEXT_SWITCH_ACTIVE_nr   1UL
-#define SPU_CONTEXT_SWITCH_PENDING     (1UL << SPU_CONTEXT_SWITCH_PENDING_nr)
-#define SPU_CONTEXT_SWITCH_ACTIVE      (1UL << SPU_CONTEXT_SWITCH_ACTIVE_nr)
+#define SPU_CONTEXT_SWITCH_PENDING     0UL
+#define SPU_CONTEXT_SWITCH_ACTIVE      1UL
 
 struct spu_context;
 struct spu_runqueue;
@@ -112,6 +110,7 @@ struct spu {
        char *name;
        unsigned long local_store_phys;
        u8 *local_store;
+       unsigned long problem_phys;
        struct spu_problem __iomem *problem;
        struct spu_priv1 __iomem *priv1;
        struct spu_priv2 __iomem *priv2;
@@ -139,6 +138,7 @@ struct spu {
        void (* wbox_callback)(struct spu *spu);
        void (* ibox_callback)(struct spu *spu);
        void (* stop_callback)(struct spu *spu);
+       void (* mfc_callback)(struct spu *spu);
 
        char irq_c0[8];
        char irq_c1[8];
@@ -149,7 +149,16 @@ struct spu *spu_alloc(void);
 void spu_free(struct spu *spu);
 int spu_irq_class_0_bottom(struct spu *spu);
 int spu_irq_class_1_bottom(struct spu *spu);
+void spu_irq_setaffinity(struct spu *spu, int cpu);
+
+/* system callbacks from the SPU */
+struct spu_syscall_block {
+       u64 nr_ret;
+       u64 parm[6];
+};
+extern long spu_sys_callback(struct spu_syscall_block *s);
 
+/* syscalls implemented in spufs */
 extern struct spufs_calls {
        asmlinkage long (*create_thread)(const char __user *name,
                                        unsigned int flags, mode_t mode);
@@ -172,6 +181,29 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
 #endif /* MODULE */
 
 
+/* access to priv1 registers */
+void spu_int_mask_and(struct spu *spu, int class, u64 mask);
+void spu_int_mask_or(struct spu *spu, int class, u64 mask);
+void spu_int_mask_set(struct spu *spu, int class, u64 mask);
+u64 spu_int_mask_get(struct spu *spu, int class);
+void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
+u64 spu_int_stat_get(struct spu *spu, int class);
+void spu_int_route_set(struct spu *spu, u64 route);
+u64 spu_mfc_dar_get(struct spu *spu);
+u64 spu_mfc_dsisr_get(struct spu *spu);
+void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
+void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
+void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
+u64 spu_mfc_sr1_get(struct spu *spu);
+void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
+u64 spu_mfc_tclass_id_get(struct spu *spu);
+void spu_tlb_invalidate(struct spu *spu);
+void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
+u64 spu_resource_allocation_groupID_get(struct spu *spu);
+void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
+u64 spu_resource_allocation_enable_get(struct spu *spu);
+
+
 /*
  * This defines the Local Store, Problem Area and Privlege Area of an SPU.
  */
@@ -377,27 +409,22 @@ struct spu_priv1 {
 #define SPU_GET_REVISION_BITS(vr)      (vr & SPU_REVISION_BITS)
        u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
 
-
        /* Interrupt Area */
-       u64 int_mask_class0_RW;                                 /* 0x100 */
+       u64 int_mask_RW[3];                                     /* 0x100 */
 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR               0x1L
 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR         0x2L
 #define CLASS0_ENABLE_SPU_ERROR_INTR                   0x4L
 #define CLASS0_ENABLE_MFC_FIR_INTR                     0x8L
-       u64 int_mask_class1_RW;                                 /* 0x108 */
 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR               0x1L
 #define CLASS1_ENABLE_STORAGE_FAULT_INTR               0x2L
 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR   0x4L
 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR   0x8L
-       u64 int_mask_class2_RW;                                 /* 0x110 */
 #define CLASS2_ENABLE_MAILBOX_INTR                     0x1L
 #define CLASS2_ENABLE_SPU_STOP_INTR                    0x2L
 #define CLASS2_ENABLE_SPU_HALT_INTR                    0x4L
 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR  0x8L
        u8  pad_0x118_0x140[0x28];                              /* 0x118 */
-       u64 int_stat_class0_RW;                                 /* 0x140 */
-       u64 int_stat_class1_RW;                                 /* 0x148 */
-       u64 int_stat_class2_RW;                                 /* 0x150 */
+       u64 int_stat_RW[3];                                     /* 0x140 */
        u8  pad_0x158_0x180[0x28];                              /* 0x158 */
        u64 int_route_RW;                                       /* 0x180 */
 
@@ -578,4 +605,5 @@ struct spu_priv1 {
        u64 spu_trace_cntl;                                     /* 0x1070 */
 } __attribute__ ((aligned(0x2000)));
 
+#endif /* __KERNEL__ */
 #endif