slab numa fallback logic: Do not pass unfiltered flags to page allocator

[linux-2.6-omap-h63xx.git] / include / asm-sh / hw_irq.h

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 4ca3f765bacc11ecf3070a3b8b0770408dd9284c..c958fdaa00957ec835f2b7b1803baef4f5eb12d7 100644 (file)
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -1,29 +1,11 @@
 #ifndef __ASM_SH_HW_IRQ_H
 #define __ASM_SH_HW_IRQ_H
 
+#include <linux/init.h>
 #include <asm/atomic.h>
 
 extern atomic_t irq_err_count;
 
-struct intc2_data {
-       unsigned short irq;
-       unsigned char ipr_offset, ipr_shift;
-       unsigned char msk_offset, msk_shift;
-       unsigned char priority;
-};
-
-struct intc2_desc {
-       unsigned long prio_base;
-       unsigned long msk_base;
-       unsigned long mskclr_base;
-       struct intc2_data *intc2_data;
-       unsigned int nr_irqs;
-       struct irq_chip chip;
-};
-
-void register_intc2_controller(struct intc2_desc *);
-void init_IRQ_intc2(void);
-
 struct ipr_data {
        unsigned char irq;
        unsigned char ipr_idx;          /* Index for the IPR registered */
@@ -40,11 +22,83 @@ struct ipr_desc {
 };
 
 void register_ipr_controller(struct ipr_desc *);
-void init_IRQ_ipr(void);
 
-/*
- * Enable individual interrupt mode for external IPR IRQs.
- */
-void ipr_irq_enable_irlm(void);
+typedef unsigned char intc_enum;
+
+struct intc_vect {
+       intc_enum enum_id;
+       unsigned short vect;
+};
+
+#define INTC_VECT(enum_id, vect) { enum_id, vect }
+#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
+
+struct intc_group {
+       intc_enum enum_id;
+       intc_enum enum_ids[32];
+};
+
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
+
+struct intc_mask_reg {
+       unsigned long set_reg, clr_reg, reg_width;
+       intc_enum enum_ids[32];
+#ifdef CONFIG_SMP
+       unsigned long smp;
+#endif
+};
+
+struct intc_prio_reg {
+       unsigned long set_reg, clr_reg, reg_width, field_width;
+       intc_enum enum_ids[16];
+#ifdef CONFIG_SMP
+       unsigned long smp;
+#endif
+};
+
+struct intc_sense_reg {
+       unsigned long reg, reg_width, field_width;
+       intc_enum enum_ids[16];
+};
+
+#ifdef CONFIG_SMP
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#else
+#define INTC_SMP(stride, nr)
+#endif
+
+struct intc_desc {
+       struct intc_vect *vectors;
+       unsigned int nr_vectors;
+       struct intc_group *groups;
+       unsigned int nr_groups;
+       struct intc_mask_reg *mask_regs;
+       unsigned int nr_mask_regs;
+       struct intc_prio_reg *prio_regs;
+       unsigned int nr_prio_regs;
+       struct intc_sense_reg *sense_regs;
+       unsigned int nr_sense_regs;
+       char *name;
+};
+
+#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,           \
+       mask_regs, prio_regs, sense_regs)                               \
+struct intc_desc symbol __initdata = {                                 \
+       _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+       _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+       _INTC_ARRAY(sense_regs),                                        \
+       chipname,                                                       \
+}
+
+void __init register_intc_controller(struct intc_desc *desc);
+int intc_set_priority(unsigned int irq, unsigned int prio);
+
+void __init plat_irq_setup(void);
+
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
+       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
+       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+void __init plat_irq_setup_pins(int mode);
 
 #endif /* __ASM_SH_HW_IRQ_H */