*/
#define __IO_PREFIX generic
#include <asm/io_generic.h>
+#include <asm/io_trapped.h>
#define maybebadio(port) \
printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
#define iowrite32(v,a) writel((v),(a))
#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
-#define ioread8_rep(a,d,c) insb((a),(d),(c))
-#define ioread16_rep(a,d,c) insw((a),(d),(c))
-#define ioread32_rep(a,d,c) insl((a),(d),(c))
+#define ioread8_rep(a, d, c) readsb((a), (d), (c))
+#define ioread16_rep(a, d, c) readsw((a), (d), (c))
+#define ioread32_rep(a, d, c) readsl((a), (d), (c))
-#define iowrite8_rep(a,s,c) outsb((a),(s),(c))
-#define iowrite16_rep(a,s,c) outsw((a),(s),(c))
-#define iowrite32_rep(a,s,c) outsl((a),(s),(c))
+#define iowrite8_rep(a, s, c) writesb((a), (s), (c))
+#define iowrite16_rep(a, s, c) writesw((a), (s), (c))
+#define iowrite32_rep(a, s, c) writesl((a), (s), (c))
#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
+#define IO_SPACE_LIMIT 0xffffffff
+
/*
* This function provides a method for the generic case where a board-specific
* ioport_map simply needs to return the port + some arbitrary port base.
generic_io_base = pbase;
}
+#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
+
/* We really want to try and get these to memcpy etc */
extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
return *(volatile unsigned long*)addr;
}
+static inline unsigned long long ctrl_inq(unsigned long addr)
+{
+ return *(volatile unsigned long long*)addr;
+}
+
static inline void ctrl_outb(unsigned char b, unsigned long addr)
{
*(volatile unsigned char*)addr = b;
*(volatile unsigned long*)addr = b;
}
-static inline void ctrl_delay(void)
+static inline void ctrl_outq(unsigned long long b, unsigned long addr)
{
- ctrl_inw(P2SEG);
+ *(volatile unsigned long long*)addr = b;
}
-#define IO_SPACE_LIMIT 0xffffffff
-
-#ifdef CONFIG_MMU
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/SuperH mapping
- */
-static inline unsigned long virt_to_phys(volatile void *address)
+static inline void ctrl_delay(void)
{
- return PHYSADDR(address);
+#ifdef P2SEG
+ ctrl_inw(P2SEG);
+#endif
}
-static inline void *phys_to_virt(unsigned long address)
-{
- return (void *)P1SEGADDR(address);
-}
-#else
-#define phys_to_virt(address) ((void *)(address))
+/* Quad-word real-mode I/O, don't ask.. */
+unsigned long long peek_real_address_q(unsigned long long addr);
+unsigned long long poke_real_address_q(unsigned long long addr,
+ unsigned long long val);
+
+#if !defined(CONFIG_MMU)
#define virt_to_phys(address) ((unsigned long)(address))
+#define phys_to_virt(address) ((void *)(address))
+#else
+#define virt_to_phys(address) (__pa(address))
+#define phys_to_virt(address) (__va(address))
#endif
/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the x86 architecture, we just read/write the
- * memory location directly.
+ * On 32-bit SH, we traditionally have the whole physical address space
+ * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
+ * not need to do anything but place the address in the proper segment.
+ * This is true for P1 and P2 addresses, as well as some P3 ones.
+ * However, most of the P3 addresses and newer cores using extended
+ * addressing need to map through page tables, so the ioremap()
+ * implementation becomes a bit more complicated.
*
- * On SH, we traditionally have the whole physical address space mapped
- * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
- * need to do anything but place the address in the proper segment. This
- * is true for P1 and P2 addresses, as well as some P3 ones. However,
- * most of the P3 addresses and newer cores using extended addressing
- * need to map through page tables, so the ioremap() implementation
- * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
- * additional notes on this.
+ * See arch/sh/mm/ioremap.c for additional notes on this.
*
* We cheat a bit and always return uncachable areas until we've fixed
* the drivers to handle caching properly.
+ *
+ * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
+ * doesn't exist, so everything must go through page tables.
*/
#ifdef CONFIG_MMU
void __iomem *__ioremap(unsigned long offset, unsigned long size,
unsigned long flags);
void __iounmap(void __iomem *addr);
+
+/* arch/sh/mm/ioremap_64.c */
+unsigned long onchip_remap(unsigned long addr, unsigned long size,
+ const char *name);
+extern void onchip_unmap(unsigned long vaddr);
#else
#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
#define __iounmap(addr) do { } while (0)
+#define onchip_remap(addr, size, name) (addr)
+#define onchip_unmap(addr) do { } while (0)
#endif /* CONFIG_MMU */
static inline void __iomem *
__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
{
+#ifdef CONFIG_SUPERH32
unsigned long last_addr = offset + size - 1;
+#endif
+ void __iomem *ret;
+
+ ret = __ioremap_trapped(offset, size);
+ if (ret)
+ return ret;
+#ifdef CONFIG_SUPERH32
/*
* For P1 and P2 space this is trivial, as everything is already
* mapped. Uncached access for P1 addresses are done through P2.
return (void __iomem *)P2SEGADDR(offset);
}
+#endif
return __ioremap(offset, size, flags);
}
projects / linux-2.6-omap-h63xx.git / blobdiff