[SPARC64]: Implement rest of generic interrupt hypervisor calls.

[linux-2.6-omap-h63xx.git] / include / asm-sparc64 / processor.h

diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
index bc1445b904efdb80a1991c895ae52ba4d067bc9b..b3889f3f943a2bda36514154c6ba76565dce6ba9 100644 (file)
--- a/include/asm-sparc64/processor.h
+++ b/include/asm-sparc64/processor.h
@@ -18,7 +18,6 @@
 #include <asm/a.out.h>
 #include <asm/pstate.h>
 #include <asm/ptrace.h>
-#include <asm/segment.h>
 #include <asm/page.h>
 
 /* The sparc has no problems with write protection */
@@ -29,6 +28,8 @@
  * User lives in his very own context, and cannot reference us. Note
  * that TASK_SIZE is a misnomer, it really gives maximum user virtual 
  * address that the kernel will allocate out.
+ *
+ * XXX No longer using virtual page tables, kill this upper limit...
  */
 #define VA_BITS                44
 #ifndef __ASSEMBLY__
@@ -38,18 +39,6 @@
 #endif
 #define TASK_SIZE      ((unsigned long)-VPTE_SIZE)
 
-/*
- * The vpte base must be able to hold the entire vpte, half
- * of which lives above, and half below, the base. And it
- * is placed as close to the highest address range as possible.
- */
-#define VPTE_BASE_SPITFIRE     (-(VPTE_SIZE/2))
-#if 1
-#define VPTE_BASE_CHEETAH      VPTE_BASE_SPITFIRE
-#else
-#define VPTE_BASE_CHEETAH      0xffe0000000000000
-#endif
-
 #ifndef __ASSEMBLY__
 
 typedef struct {
@@ -187,11 +176,46 @@ extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 
 extern unsigned long get_wchan(struct task_struct *task);
 
-#define KSTK_EIP(tsk)  ((tsk)->thread_info->kregs->tpc)
-#define KSTK_ESP(tsk)  ((tsk)->thread_info->kregs->u_regs[UREG_FP])
+#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->tpc)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->u_regs[UREG_FP])
 
 #define cpu_relax()    barrier()
 
+/* Prefetch support.  This is tuned for UltraSPARC-III and later.
+ * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
+ * a shallower prefetch queue than later chips.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+static inline void prefetch(const void *x)
+{
+       /* We do not use the read prefetch mnemonic because that
+        * prefetches into the prefetch-cache which only is accessible
+        * by floating point operations in UltraSPARC-III and later.
+        * By contrast, "#one_write" prefetches into the L2 cache
+        * in shared state.
+        */
+       __asm__ __volatile__("prefetch [%0], #one_write"
+                            : /* no outputs */
+                            : "r" (x));
+}
+
+static inline void prefetchw(const void *x)
+{
+       /* The most optimal prefetch to use for writes is
+        * "#n_writes".  This brings the cacheline into the
+        * L2 cache in "owned" state.
+        */
+       __asm__ __volatile__("prefetch [%0], #n_writes"
+                            : /* no outputs */
+                            : "r" (x));
+}
+
+#define spin_lock_prefetch(x)  prefetchw(x)
+
 #endif /* !(__ASSEMBLY__) */
 
 #endif /* !(__ASM_SPARC64_PROCESSOR_H) */