sparc: Merge include/asm-sparc{,64}/openpromio.h

[linux-2.6-omap-h63xx.git] / include / asm-sparc64 / spitfire.h

diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index cf7807813e85fe976e9113cfea4a51fd7ac855c1..985ea7e319927d2e7906c13956cd95dc5354289e 100644 (file)
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -1,7 +1,6 @@
-/* $Id: spitfire.h,v 1.18 2001/11/29 16:42:10 kanoj Exp $
- * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
+/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
  *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
 
 #ifndef _SPARC64_SPITFIRE_H
@@ -64,10 +63,12 @@ extern void cheetah_enable_pcache(void);
         SPITFIRE_HIGHEST_LOCKED_TLBENT : \
         CHEETAH_HIGHEST_LOCKED_TLBENT)
 
+extern int num_kernel_image_mappings;
+
 /* The data cache is write through, so this just invalidates the
  * specified line.
  */
-static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
+static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -81,7 +82,7 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
  * a flush instruction (to any address) is sufficient to handle
  * this issue after the line is invalidated.
  */
-static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
+static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -89,7 +90,7 @@ static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long
                             : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
 }
 
-static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
+static inline unsigned long spitfire_get_dtlb_data(int entry)
 {
        unsigned long data;
 
@@ -103,7 +104,7 @@ static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
        return data;
 }
 
-static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
+static inline unsigned long spitfire_get_dtlb_tag(int entry)
 {
        unsigned long tag;
 
@@ -113,7 +114,7 @@ static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
        return tag;
 }
 
-static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
+static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -122,7 +123,7 @@ static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
                               "i" (ASI_DTLB_DATA_ACCESS));
 }
 
-static __inline__ unsigned long spitfire_get_itlb_data(int entry)
+static inline unsigned long spitfire_get_itlb_data(int entry)
 {
        unsigned long data;
 
@@ -136,7 +137,7 @@ static __inline__ unsigned long spitfire_get_itlb_data(int entry)
        return data;
 }
 
-static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
+static inline unsigned long spitfire_get_itlb_tag(int entry)
 {
        unsigned long tag;
 
@@ -146,7 +147,7 @@ static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
        return tag;
 }
 
-static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
+static inline void spitfire_put_itlb_data(int entry, unsigned long data)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -155,7 +156,7 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
                               "i" (ASI_ITLB_DATA_ACCESS));
 }
 
-static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
+static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
 {
        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
                             "membar    #Sync"
@@ -163,7 +164,7 @@ static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
                             : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
 }
 
-static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
+static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
 {
        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
                             "membar    #Sync"
@@ -172,7 +173,7 @@ static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
 }
 
 /* Cheetah has "all non-locked" tlb flushes. */
-static __inline__ void cheetah_flush_dtlb_all(void)
+static inline void cheetah_flush_dtlb_all(void)
 {
        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
                             "membar    #Sync"
@@ -180,7 +181,7 @@ static __inline__ void cheetah_flush_dtlb_all(void)
                             : "r" (0x80), "i" (ASI_DMMU_DEMAP));
 }
 
-static __inline__ void cheetah_flush_itlb_all(void)
+static inline void cheetah_flush_itlb_all(void)
 {
        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
                             "membar    #Sync"
@@ -202,7 +203,7 @@ static __inline__ void cheetah_flush_itlb_all(void)
  * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
  * the problem for me. -DaveM
  */
-static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
+static inline unsigned long cheetah_get_ldtlb_data(int entry)
 {
        unsigned long data;
 
@@ -215,7 +216,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
        return data;
 }
 
-static __inline__ unsigned long cheetah_get_litlb_data(int entry)
+static inline unsigned long cheetah_get_litlb_data(int entry)
 {
        unsigned long data;
 
@@ -228,7 +229,7 @@ static __inline__ unsigned long cheetah_get_litlb_data(int entry)
        return data;
 }
 
-static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
+static inline unsigned long cheetah_get_ldtlb_tag(int entry)
 {
        unsigned long tag;
 
@@ -240,7 +241,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
        return tag;
 }
 
-static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
+static inline unsigned long cheetah_get_litlb_tag(int entry)
 {
        unsigned long tag;
 
@@ -252,7 +253,7 @@ static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
        return tag;
 }
 
-static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
+static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -262,7 +263,7 @@ static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
                               "i" (ASI_DTLB_DATA_ACCESS));
 }
 
-static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
+static inline void cheetah_put_litlb_data(int entry, unsigned long data)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -272,7 +273,7 @@ static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
                               "i" (ASI_ITLB_DATA_ACCESS));
 }
 
-static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
+static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
 {
        unsigned long data;
 
@@ -284,7 +285,7 @@ static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
        return data;
 }
 
-static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
+static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
 {
        unsigned long tag;
 
@@ -294,7 +295,7 @@ static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
        return tag;
 }
 
-static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
+static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"
@@ -304,7 +305,7 @@ static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int
                               "i" (ASI_DTLB_DATA_ACCESS));
 }
 
-static __inline__ unsigned long cheetah_get_itlb_data(int entry)
+static inline unsigned long cheetah_get_itlb_data(int entry)
 {
        unsigned long data;
 
@@ -317,7 +318,7 @@ static __inline__ unsigned long cheetah_get_itlb_data(int entry)
        return data;
 }
 
-static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
+static inline unsigned long cheetah_get_itlb_tag(int entry)
 {
        unsigned long tag;
 
@@ -327,7 +328,7 @@ static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
        return tag;
 }
 
-static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data)
+static inline void cheetah_put_itlb_data(int entry, unsigned long data)
 {
        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                             "membar    #Sync"