[ARM] fix cache alignment code in memset.S

[linux-2.6-omap-h63xx.git] / include / asm-x86 / hw_irq_64.h

diff --git a/include/asm-x86/hw_irq_64.h b/include/asm-x86/hw_irq_64.h
index 312a58d6dac65cc96e4b4e0fd519650143c6c58a..0062ef390f6771e145362a533db176e1cf78523d 100644 (file)
--- a/include/asm-x86/hw_irq_64.h
+++ b/include/asm-x86/hw_irq_64.h
@@ -36,7 +36,7 @@
  * cleanup after irq migration.
  */
 #define IRQ_MOVE_CLEANUP_VECTOR        FIRST_EXTERNAL_VECTOR
- 
+
 /*
  * Vectors 0x30-0x3f are used for ISA interrupts.
  */
@@ -159,13 +159,12 @@ extern atomic_t irq_mis_count;
  *     SMP has a few special interrupts for IPI messages
  */
 
-#define BUILD_IRQ(nr) \
-asmlinkage void IRQ_NAME(nr); \
-__asm__( \
-"\n.p2align\n" \
-"IRQ" #nr "_interrupt:\n\t" \
-       "push $~(" #nr ") ; " \
-       "jmp common_interrupt");
+#define BUILD_IRQ(nr)                          \
+       asmlinkage void IRQ_NAME(nr);           \
+       asm("\n.p2align\n"                      \
+           "IRQ" #nr "_interrupt:\n\t"         \
+           "push $~(" #nr ") ; "               \
+           "jmp common_interrupt");
 
 #define platform_legacy_irq(irq)       ((irq) < 16)