Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6

[linux-2.6-omap-h63xx.git] / include / asm-x86 / msr-index.h

diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index a4944732be04d9fa1a75d66ab5799f8f96be6eda..09413ad39d3c8db4aeb42edcedd1a38d6e3779a6 100644 (file)
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -57,12 +57,21 @@
 #define MSR_MTRRfix4K_F8000            0x0000026f
 #define MSR_MTRRdefType                        0x000002ff
 
+#define MSR_IA32_CR_PAT                        0x00000277
+
 #define MSR_IA32_DEBUGCTLMSR           0x000001d9
 #define MSR_IA32_LASTBRANCHFROMIP      0x000001db
 #define MSR_IA32_LASTBRANCHTOIP                0x000001dc
 #define MSR_IA32_LASTINTFROMIP         0x000001dd
 #define MSR_IA32_LASTINTTOIP           0x000001de
 
+/* DEBUGCTLMSR bits (others vary by model): */
+#define _DEBUGCTLMSR_LBR       0 /* last branch recording */
+#define _DEBUGCTLMSR_BTF       1 /* single-step on branches */
+
+#define DEBUGCTLMSR_LBR                (1UL << _DEBUGCTLMSR_LBR)
+#define DEBUGCTLMSR_BTF                (1UL << _DEBUGCTLMSR_BTF)
+
 #define MSR_IA32_MC0_CTL               0x00000400
 #define MSR_IA32_MC0_STATUS            0x00000401
 #define MSR_IA32_MC0_ADDR              0x00000402
@@ -76,6 +85,7 @@
 /* AMD64 MSRs. Not complete. See the architecture manual for a more
    complete list. */
 
+#define MSR_AMD64_NB_CFG               0xc001001f
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
 #define MSR_AMD64_IBSFETCHPHYSAD       0xc0011032
@@ -88,12 +98,21 @@
 #define MSR_AMD64_IBSDCPHYSAD          0xc0011039
 #define MSR_AMD64_IBSCTL               0xc001103a
 
+/* Fam 10h MSRs */
+#define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
+#define FAM10H_MMIO_CONF_ENABLE                (1<<0)
+#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
+#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
+#define FAM10H_MMIO_CONF_BASE_MASK     0xfffffff
+#define FAM10H_MMIO_CONF_BASE_SHIFT    20
+
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a
 #define MSR_K8_TOP_MEM2                        0xc001001d
 #define MSR_K8_SYSCFG                  0xc0010010
 #define MSR_K8_HWCR                    0xc0010015
 #define MSR_K8_ENABLE_C1E              0xc0010055
+#define MSR_K8_TSEG_ADDR               0xc0010112
 #define K8_MTRRFIXRANGE_DRAM_ENABLE    0x00040000 /* MtrrFixDramEn bit    */
 #define K8_MTRRFIXRANGE_DRAM_MODIFY    0x00080000 /* MtrrFixDramModEn bit */
 #define K8_MTRR_RDMEM_WRMEM_MASK       0x18181818 /* Mask: RdMem|WrMem    */