DSPGW: Use ALIGN macro instead of homemade one

[linux-2.6-omap-h63xx.git] / include / asm-x86_64 / tlbflush.h

diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index d16d5b60f419b4680d20bd14bb7b93bba8f74308..888eb4abdd07a2fffa1c3ca3486962a3b56d7be5 100644 (file)
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -2,46 +2,24 @@
 #define _X8664_TLBFLUSH_H
 
 #include <linux/mm.h>
+#include <linux/sched.h>
 #include <asm/processor.h>
+#include <asm/system.h>
 
-#define __flush_tlb()                                                  \
-       do {                                                            \
-               unsigned long tmpreg;                                   \
-                                                                       \
-               __asm__ __volatile__(                                   \
-                       "movq %%cr3, %0;  # flush TLB \n"               \
-                       "movq %0, %%cr3;              \n"               \
-                       : "=r" (tmpreg)                                 \
-                       :: "memory");                                   \
-       } while (0)
+static inline void __flush_tlb(void)
+{
+       write_cr3(read_cr3());
+}
 
-/*
- * Global pages have to be flushed a bit differently. Not a real
- * performance problem because this does not happen often.
- */
-#define __flush_tlb_global()                                           \
-       do {                                                            \
-               unsigned long tmpreg, cr4, cr4_orig;                    \
-                                                                       \
-               __asm__ __volatile__(                                   \
-                       "movq %%cr4, %2;  # turn off PGE     \n"        \
-                       "movq %2, %1;                        \n"        \
-                       "andq %3, %1;                        \n"        \
-                       "movq %1, %%cr4;                     \n"        \
-                       "movq %%cr3, %0;  # flush TLB        \n"        \
-                       "movq %0, %%cr3;                     \n"        \
-                       "movq %2, %%cr4;  # turn PGE back on \n"        \
-                       : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
-                       : "i" (~X86_CR4_PGE)                            \
-                       : "memory");                                    \
-       } while (0)
-
-extern unsigned long pgkern_mask;
-
-#define __flush_tlb_all() __flush_tlb_global()
+static inline void __flush_tlb_all(void)
+{
+       unsigned long cr4 = read_cr4();
+       write_cr4(cr4 & ~X86_CR4_PGE);  /* clear PGE */
+       write_cr4(cr4);                 /* write old PGE again and flush TLBs */
+}
 
 #define __flush_tlb_one(addr) \
-       __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
+       __asm__ __volatile__("invlpg (%0)" :: "r" (addr) : "memory")
 
 
 /*
@@ -114,7 +92,11 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
 
 #endif
 
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                       unsigned long end)
+{
+       flush_tlb_all();
+}
 
 static inline void flush_tlb_pgtables(struct mm_struct *mm,
                                      unsigned long start, unsigned long end)