Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...

[linux-2.6-omap-h63xx.git] / include / linux / ssb / ssb_driver_chipcommon.h

diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
index 4cb99549466297a9021a482f14dafdab79048e73..7d7e03dcf77c4914d9490069012a9299cba42638 100644 (file)
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -51,9 +51,12 @@
 #define  SSB_CHIPCO_CAP_JTAGM          0x00400000      /* JTAG master present */
 #define  SSB_CHIPCO_CAP_BROM           0x00800000      /* Internal boot ROM active */
 #define  SSB_CHIPCO_CAP_64BIT          0x08000000      /* 64-bit Backplane */
+#define  SSB_CHIPCO_CAP_PMU            0x10000000      /* PMU available (rev >= 20) */
+#define  SSB_CHIPCO_CAP_ECI            0x20000000      /* ECI available (rev >= 20) */
 #define SSB_CHIPCO_CORECTL             0x0008
 #define  SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001      /* Drive UART with internal clock */
 #define         SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
+#define  SSB_CHIPCO_CORECTL_UARTCLKEN  0x00000008      /* UART clock enable (rev >= 21) */
 #define SSB_CHIPCO_BIST                        0x000C
 #define SSB_CHIPCO_OTPS                        0x0010          /* OTP status */
 #define         SSB_CHIPCO_OTPS_PROGFAIL       0x80000000
@@ -357,10 +360,14 @@ struct ssb_chipcommon {
        u16 fast_pwrup_delay;
 };
 
+static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
+{
+       return (cc->dev != NULL);
+}
+
 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
 
-#include <linux/pm.h>
-extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
+extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
 extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
 
 extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
@@ -382,11 +389,17 @@ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
 extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
                                          u32 ticks);
 
-u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
+void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
 
-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
+u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask);
 
-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
+/* Chipcommon GPIO pin access. */
+u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
 
 #ifdef CONFIG_SSB_SERIAL
 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,