X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fpci%2Fsetup-bus.c;h=f9b7bdd278292c633717ecfe0eb265a1ed97a864;hb=bda0c0afa7a694bb1459fd023515aca681e4d79a;hp=125e7b7f34ffd13462e551b31c79cd03ab0d3572;hpb=9ef64cb4320df821638b508f79aa8b858cca99f0;p=linux-2.6-omap-h63xx.git diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 125e7b7f34f..f9b7bdd2782 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -65,6 +65,7 @@ static void pbus_assign_resources_sorted(struct pci_bus *bus) res = list->res; idx = res - &list->dev->resource[0]; if (pci_assign_resource(list->dev, idx)) { + /* FIXME: get rid of this */ res->start = 0; res->end = 0; res->flags = 0; @@ -144,8 +145,7 @@ EXPORT_SYMBOL(pci_setup_cardbus); config space writes, so it's quite possible that an I/O window of the bridge will have some undesirable address (e.g. 0) after the first write. Ditto 64-bit prefetchable MMIO. */ -static void __devinit -pci_setup_bridge(struct pci_bus *bus) +static void pci_setup_bridge(struct pci_bus *bus) { struct pci_dev *bridge = bus->self; struct pci_bus_region region; @@ -327,6 +327,7 @@ static void pbus_size_io(struct pci_bus *bus) /* Alignment of the IO window is always 4K */ b_res->start = 4096; b_res->end = b_res->start + size - 1; + b_res->flags |= IORESOURCE_STARTALIGN; } /* Calculate the size of the bus and minimal alignment which @@ -401,11 +402,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long } b_res->start = min_align; b_res->end = size + min_align - 1; + b_res->flags |= IORESOURCE_STARTALIGN; return 1; } -static void __devinit -pci_bus_size_cardbus(struct pci_bus *bus) +static void pci_bus_size_cardbus(struct pci_bus *bus) { struct pci_dev *bridge = bus->self; struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; @@ -486,12 +487,7 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus) break; case PCI_CLASS_BRIDGE_PCI: - /* don't size subtractive decoding (transparent) - * PCI-to-PCI bridges */ - if (bus->self->transparent) - break; pci_bridge_check_ranges(bus); - /* fall through */ default: pbus_size_io(bus); /* If the bridge supports prefetchable range, size it