X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-omap2%2Fpm.c;h=a7faba3d91823f7e1f0f8a0d87be9ce572fa6b78;hb=9d0cbf9442c08a413bafbddb3e0f2cc5a3522bf8;hp=f9fd3e3d0a59dfa4e300a1a64ac1cb6f6601ac02;hpb=95d9ffbe01fb21d524c86bf77871255066bc6e55;p=linux-2.6-omap-h63xx.git diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index f9fd3e3d0a5..a7faba3d918 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -3,11 +3,15 @@ * * OMAP2 Power Management Routines * - * Copyright (C) 2006 Nokia Corporation - * Tony Lindgren - * * Copyright (C) 2005 Texas Instruments, Inc. + * Copyright (C) 2006-2008 Nokia Corporation + * + * Written by: * Richard Woodruff + * Tony Lindgren + * Juha Yrjola + * Amit Kucheria + * Igor Stoppa * * Based on pm.c for omap1 * @@ -23,6 +27,7 @@ #include #include #include +#include #include #include @@ -34,307 +39,578 @@ #include #include #include +#include +#include #include +#include +#include +#include + +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" -#include "prcm-regs.h" +/* These addrs are in assembly language code to be patched at runtime */ +extern void *omap2_ocs_sdrc_power; +extern void *omap2_ocs_sdrc_dlla_ctrl; -static struct clk *vclk; static void (*omap2_sram_idle)(void); -static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); +static void (*omap2_sram_suspend)(void __iomem *dllctrl); static void (*saved_idle)(void); -extern void __init pmdomain_init(void); -extern void pmdomain_set_autoidle(void); +static u32 omap2_read_32k_sync_counter(void) +{ + return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010); +} + +#ifdef CONFIG_PM_DEBUG +int omap2_pm_debug = 0; + +static int serial_console_clock_disabled; +static int serial_console_uart; +static unsigned int serial_console_next_disable; -static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE]; +static struct clk *console_iclk, *console_fclk; -void omap2_pm_idle(void) +static void serial_console_kick(void) { - local_irq_disable(); - local_fiq_disable(); - if (need_resched()) { - local_fiq_enable(); - local_irq_enable(); - return; - } + serial_console_next_disable = omap2_read_32k_sync_counter(); + /* Keep the clocks on for 4 secs */ + serial_console_next_disable += 4 * 32768; +} - /* - * Since an interrupt may set up a timer, we don't want to - * reprogram the hardware timer with interrupts enabled. - * Re-enable interrupts only after returning from idle. - */ - timer_dyn_reprogram(); +static void serial_wait_tx(void) +{ + static const unsigned long uart_bases[3] = { + 0x4806a000, 0x4806c000, 0x4806e000 + }; + unsigned long lsr_reg; + int looped = 0; + + /* Wait for TX FIFO and THR to get empty */ + lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2)); + while ((__raw_readb(lsr_reg) & 0x60) != 0x60) + looped = 1; + if (looped) + serial_console_kick(); +} - omap2_sram_idle(); - local_fiq_enable(); - local_irq_enable(); +static void serial_console_fclk_mask(u32 *f1, u32 *f2) +{ + switch (serial_console_uart) { + case 1: + *f1 &= ~(1 << 21); + break; + case 2: + *f1 &= ~(1 << 22); + break; + case 3: + *f2 &= ~(1 << 2); + break; + } } -static int omap2_pm_prepare(suspend_state_t state) +static void serial_console_sleep(int enable) { - int error = 0; + if (console_iclk == NULL || console_fclk == NULL) + return; - /* We cannot sleep in idle until we have resumed */ - saved_idle = pm_idle; - pm_idle = NULL; + if (enable) { + BUG_ON(serial_console_clock_disabled); + if (clk_get_usecount(console_fclk) == 0) + return; + if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0) + return; + serial_wait_tx(); + clk_disable(console_iclk); + clk_disable(console_fclk); + serial_console_clock_disabled = 1; + } else { + int serial_wakeup = 0; + u32 l; + + switch (serial_console_uart) { + case 1: + l = prm_read_mod_reg(CORE_MOD, PM_WKST1); + if (l & OMAP24XX_ST_UART1) + serial_wakeup = 1; + break; + case 2: + l = prm_read_mod_reg(CORE_MOD, PM_WKST1); + if (l & OMAP24XX_ST_UART2) + serial_wakeup = 1; + break; + case 3: + l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2); + if (l & OMAP24XX_ST_UART3) + serial_wakeup = 1; + break; + } + if (serial_wakeup) + serial_console_kick(); + if (!serial_console_clock_disabled) + return; + clk_enable(console_iclk); + clk_enable(console_fclk); + serial_console_clock_disabled = 0; + } +} - switch (state) - { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: +static void pm_init_serial_console(void) +{ + const struct omap_serial_console_config *conf; + char name[16]; + + conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE, + struct omap_serial_console_config); + if (conf == NULL) + return; + if (conf->console_uart > 3 || conf->console_uart < 1) + return; + serial_console_uart = conf->console_uart; + sprintf(name, "uart%d_fck", conf->console_uart); + console_fclk = clk_get(NULL, name); + if (IS_ERR(console_fclk)) + console_fclk = NULL; + name[6] = 'i'; + console_iclk = clk_get(NULL, name); + if (IS_ERR(console_fclk)) + console_iclk = NULL; + if (console_fclk == NULL || console_iclk == NULL) { + serial_console_uart = 0; + return; + } + switch (serial_console_uart) { + case 1: + prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1); + break; + case 2: + prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1); break; + case 3: + prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2); + break; + } +} - default: - return -EINVAL; +#define DUMP_PRM_MOD_REG(mod, reg) \ + regs[reg_count].name = #mod "." #reg; \ + regs[reg_count++].val = prm_read_mod_reg(mod, reg) +#define DUMP_CM_MOD_REG(mod, reg) \ + regs[reg_count].name = #mod "." #reg; \ + regs[reg_count++].val = cm_read_mod_reg(mod, reg) +#define DUMP_PRM_REG(reg) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = __raw_readl(reg) +#define DUMP_CM_REG(reg) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = __raw_readl(reg) +#define DUMP_INTC_REG(reg, off) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) + +static void omap2_pm_dump(int mode, int resume, unsigned int us) +{ + struct reg { + const char *name; + u32 val; + } regs[32]; + int reg_count = 0, i; + const char *s1 = NULL, *s2 = NULL; + + if (!resume) { +#if 0 + /* MPU */ + DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU); + DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); +#endif +#if 0 + /* INTC */ + DUMP_INTC_REG(INTC_MIR0, 0x0084); + DUMP_INTC_REG(INTC_MIR1, 0x00a4); + DUMP_INTC_REG(INTC_MIR2, 0x00c4); +#endif +#if 0 + DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); + DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2); + DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN); + DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); + DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); + DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); + DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); + DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL); + DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); + DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); + DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL); +#endif +#if 0 + /* DSP */ + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); +#endif + } else { + DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); + DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); + DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST); + DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU); +#if 1 + DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098); + DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8); + DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8); +#endif } - return error; + switch (mode) { + case 0: + s1 = "full"; + s2 = "retention"; + break; + case 1: + s1 = "MPU"; + s2 = "retention"; + break; + case 2: + s1 = "MPU"; + s2 = "idle"; + break; + } + + if (!resume) +#if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ) + printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2, + jiffies_to_msecs(get_next_timer_interrupt(jiffies) - + jiffies)); +#else + printk("--- Going to %s %s\n", s1, s2); +#endif + else + printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000); + for (i = 0; i < reg_count; i++) + printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val); } -#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \ - OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \ - OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3)) +#else +static inline void serial_console_sleep(int enable) {} +static inline void pm_init_serial_console(void) {} +static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {} +static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {} -#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4)) +#define omap2_pm_debug 0 -#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \ - OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \ - OMAP_IRQ_BIT(INT_24XX_UART3_IRQ)) +#endif -#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, ®, reg); +static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */ -static void omap2_pm_debug(char * desc) +static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) { - printk("%s:\n", desc); - - preg(CM_CLKSTCTRL_MPU); - preg(CM_CLKSTCTRL_CORE); - preg(CM_CLKSTCTRL_GFX); - preg(CM_CLKSTCTRL_DSP); - preg(CM_CLKSTCTRL_MDM); - - preg(PM_PWSTCTRL_MPU); - preg(PM_PWSTCTRL_CORE); - preg(PM_PWSTCTRL_GFX); - preg(PM_PWSTCTRL_DSP); - preg(PM_PWSTCTRL_MDM); - - preg(PM_PWSTST_MPU); - preg(PM_PWSTST_CORE); - preg(PM_PWSTST_GFX); - preg(PM_PWSTST_DSP); - preg(PM_PWSTST_MDM); - - preg(CM_AUTOIDLE1_CORE); - preg(CM_AUTOIDLE2_CORE); - preg(CM_AUTOIDLE3_CORE); - preg(CM_AUTOIDLE4_CORE); - preg(CM_AUTOIDLE_WKUP); - preg(CM_AUTOIDLE_PLL); - preg(CM_AUTOIDLE_DSP); - preg(CM_AUTOIDLE_MDM); - - preg(CM_ICLKEN1_CORE); - preg(CM_ICLKEN2_CORE); - preg(CM_ICLKEN3_CORE); - preg(CM_ICLKEN4_CORE); - preg(CM_ICLKEN_GFX); - preg(CM_ICLKEN_WKUP); - preg(CM_ICLKEN_DSP); - preg(CM_ICLKEN_MDM); - - preg(CM_IDLEST1_CORE); - preg(CM_IDLEST2_CORE); - preg(CM_IDLEST3_CORE); - preg(CM_IDLEST4_CORE); - preg(CM_IDLEST_GFX); - preg(CM_IDLEST_WKUP); - preg(CM_IDLEST_CKGEN); - preg(CM_IDLEST_DSP); - preg(CM_IDLEST_MDM); - - preg(RM_RSTST_MPU); - preg(RM_RSTST_GFX); - preg(RM_RSTST_WKUP); - preg(RM_RSTST_DSP); - preg(RM_RSTST_MDM); - - preg(PM_WKDEP_MPU); - preg(PM_WKDEP_CORE); - preg(PM_WKDEP_GFX); - preg(PM_WKDEP_DSP); - preg(PM_WKDEP_MDM); - - preg(CM_FCLKEN_WKUP); - preg(CM_ICLKEN_WKUP); - preg(CM_IDLEST_WKUP); - preg(CM_AUTOIDLE_WKUP); - preg(CM_CLKSEL_WKUP); - - preg(PM_WKEN_WKUP); - preg(PM_WKST_WKUP); + return sprintf(buf, "%hu\n", enable_dyn_sleep); } -static inline void omap2_pm_save_registers(void) +static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, + const char * buf, size_t n) { - /* Save interrupt registers */ - OMAP24XX_SAVE(INTC_MIR0); - OMAP24XX_SAVE(INTC_MIR1); - OMAP24XX_SAVE(INTC_MIR2); - - /* Save power control registers */ - OMAP24XX_SAVE(CM_CLKSTCTRL_MPU); - OMAP24XX_SAVE(CM_CLKSTCTRL_CORE); - OMAP24XX_SAVE(CM_CLKSTCTRL_GFX); - OMAP24XX_SAVE(CM_CLKSTCTRL_DSP); - OMAP24XX_SAVE(CM_CLKSTCTRL_MDM); - - /* Save power state registers */ - OMAP24XX_SAVE(PM_PWSTCTRL_MPU); - OMAP24XX_SAVE(PM_PWSTCTRL_CORE); - OMAP24XX_SAVE(PM_PWSTCTRL_GFX); - OMAP24XX_SAVE(PM_PWSTCTRL_DSP); - OMAP24XX_SAVE(PM_PWSTCTRL_MDM); - - /* Save autoidle registers */ - OMAP24XX_SAVE(CM_AUTOIDLE1_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE2_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE3_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE4_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE_WKUP); - OMAP24XX_SAVE(CM_AUTOIDLE_PLL); - OMAP24XX_SAVE(CM_AUTOIDLE_DSP); - OMAP24XX_SAVE(CM_AUTOIDLE_MDM); - - /* Save idle state registers */ - OMAP24XX_SAVE(CM_IDLEST1_CORE); - OMAP24XX_SAVE(CM_IDLEST2_CORE); - OMAP24XX_SAVE(CM_IDLEST3_CORE); - OMAP24XX_SAVE(CM_IDLEST4_CORE); - OMAP24XX_SAVE(CM_IDLEST_GFX); - OMAP24XX_SAVE(CM_IDLEST_WKUP); - OMAP24XX_SAVE(CM_IDLEST_CKGEN); - OMAP24XX_SAVE(CM_IDLEST_DSP); - OMAP24XX_SAVE(CM_IDLEST_MDM); - - /* Save clock registers */ - OMAP24XX_SAVE(CM_FCLKEN1_CORE); - OMAP24XX_SAVE(CM_FCLKEN2_CORE); - OMAP24XX_SAVE(CM_ICLKEN1_CORE); - OMAP24XX_SAVE(CM_ICLKEN2_CORE); - OMAP24XX_SAVE(CM_ICLKEN3_CORE); - OMAP24XX_SAVE(CM_ICLKEN4_CORE); + unsigned short value; + if (sscanf(buf, "%hu", &value) != 1 || + (value != 0 && value != 1)) { + printk(KERN_ERR "idle_sleep_store: Invalid value\n"); + return -EINVAL; + } + enable_dyn_sleep = value; + return n; } -static inline void omap2_pm_restore_registers(void) +static struct kobj_attribute sleep_while_idle_attr = + __ATTR(sleep_while_idle, 0644, idle_show, idle_store); + +static struct clk *osc_ck, *emul_ck; + +static int omap2_fclks_active(void) { - /* Restore clock state registers */ - OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU); - OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE); - OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX); - OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP); - OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM); - - /* Restore power state registers */ - OMAP24XX_RESTORE(PM_PWSTCTRL_MPU); - OMAP24XX_RESTORE(PM_PWSTCTRL_CORE); - OMAP24XX_RESTORE(PM_PWSTCTRL_GFX); - OMAP24XX_RESTORE(PM_PWSTCTRL_DSP); - OMAP24XX_RESTORE(PM_PWSTCTRL_MDM); - - /* Restore idle state registers */ - OMAP24XX_RESTORE(CM_IDLEST1_CORE); - OMAP24XX_RESTORE(CM_IDLEST2_CORE); - OMAP24XX_RESTORE(CM_IDLEST3_CORE); - OMAP24XX_RESTORE(CM_IDLEST4_CORE); - OMAP24XX_RESTORE(CM_IDLEST_GFX); - OMAP24XX_RESTORE(CM_IDLEST_WKUP); - OMAP24XX_RESTORE(CM_IDLEST_CKGEN); - OMAP24XX_RESTORE(CM_IDLEST_DSP); - OMAP24XX_RESTORE(CM_IDLEST_MDM); - - /* Restore autoidle registers */ - OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP); - OMAP24XX_RESTORE(CM_AUTOIDLE_PLL); - OMAP24XX_RESTORE(CM_AUTOIDLE_DSP); - OMAP24XX_RESTORE(CM_AUTOIDLE_MDM); - - /* Restore clock registers */ - OMAP24XX_RESTORE(CM_FCLKEN1_CORE); - OMAP24XX_RESTORE(CM_FCLKEN2_CORE); - OMAP24XX_RESTORE(CM_ICLKEN1_CORE); - OMAP24XX_RESTORE(CM_ICLKEN2_CORE); - OMAP24XX_RESTORE(CM_ICLKEN3_CORE); - OMAP24XX_RESTORE(CM_ICLKEN4_CORE); - - /* REVISIT: Clear interrupts here */ - - /* Restore interrupt registers */ - OMAP24XX_RESTORE(INTC_MIR0); - OMAP24XX_RESTORE(INTC_MIR1); - OMAP24XX_RESTORE(INTC_MIR2); + u32 f1, f2; + + f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + serial_console_fclk_mask(&f1, &f2); + if (f1 | f2) + return 1; + return 0; } -static int omap2_pm_suspend(void) +static int omap2_irq_pending(void) { - int processor_type = 0; + u32 pending_reg = IO_ADDRESS(0x480fe098); + int i; - /* REVISIT: 0x21 or 0x26? */ - if (cpu_is_omap2420()) - processor_type = 0x21; + for (i = 0; i < 4; i++) { + if (__raw_readl(pending_reg)) + return 1; + pending_reg += 0x20; + } + return 0; +} - if (!processor_type) - return -ENOTSUPP; +static atomic_t sleep_block = ATOMIC_INIT(0); - local_irq_disable(); - local_fiq_disable(); +void omap2_block_sleep(void) +{ + atomic_inc(&sleep_block); +} - omap2_pm_save_registers(); +void omap2_allow_sleep(void) +{ + int i; - /* Disable interrupts except for the wake events */ - INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK; - INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK; - INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK; + i = atomic_dec_return(&sleep_block); + BUG_ON(i < 0); +} - pmdomain_set_autoidle(); +static void omap2_enter_full_retention(void) +{ + u32 l, sleep_time = 0; + + /* There is 1 reference hold for all children of the oscillator + * clock, the following will remove it. If no one else uses the + * oscillator itself it will be disabled if/when we enter retention + * mode. + */ + clk_disable(osc_ck); /* Clear old wake-up events */ - PM_WKST1_CORE = 0; - PM_WKST2_CORE = 0; - PM_WKST_WKUP = 0; + /* REVISIT: These write to reserved bits? */ + prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - /* Enable wake-up events */ - PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */ - PM_WKEN2_CORE = (1 << 2); /* UART3 */ - PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */ + /* Try to enter retention */ + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + + /* Workaround to kill USB */ + l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; + omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); + + omap2_gpio_prepare_for_retention(); - /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled - * in the SRAM suspend code */ - CM_FCLKEN1_CORE = 0; - CM_FCLKEN2_CORE = 0; - CM_ICLKEN1_CORE = 0; - CM_ICLKEN3_CORE = 0; - CM_ICLKEN4_CORE = 0; + if (omap2_pm_debug) { + omap2_pm_dump(0, 0, 0); + sleep_time = omap2_read_32k_sync_counter(); + } + + /* One last check for pending IRQs to avoid extra latency due + * to sleeping unnecessarily. */ + if (omap2_irq_pending()) + goto no_sleep; + + serial_console_sleep(1); + /* Jump to SRAM suspend code */ + omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); +no_sleep: + serial_console_sleep(0); + + if (omap2_pm_debug) { + unsigned long long tmp; + u32 resume_time; + + resume_time = omap2_read_32k_sync_counter(); + tmp = resume_time - sleep_time; + tmp *= 1000000; + omap2_pm_dump(0, 1, tmp / 32768); + } + omap2_gpio_resume_after_retention(); + + clk_enable(osc_ck); + + /* clear CORE wake-up events */ + prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + + /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ + prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + + /* MPU domain wake events */ + l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU); + if (l & 0x01) + __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU); + if (l & 0x20) + __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU); + + /* Mask future PRCM-to-MPU interrupts */ + __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU); +} + +static int omap2_i2c_active(void) +{ + u32 l; + + l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); +} + +static int sti_console_enabled; + +static int omap2_allow_mpu_retention(void) +{ + u32 l; + + if (atomic_read(&sleep_block)) + return 0; + + /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ + l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | + OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | + OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) + return 0; + /* Check for UART3. */ + l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + if (l & OMAP24XX_EN_UART3) + return 0; + if (sti_console_enabled) + return 0; + + return 1; +} - omap2_pm_debug("Status before suspend"); +static void omap2_enter_mpu_retention(void) +{ + u32 sleep_time = 0; + int only_idle = 0; - /* Must wait for serial buffers to clear */ - mdelay(200); + /* Putting MPU into the WFI state while a transfer is active + * seems to cause the I2C block to timeout. Why? Good question. */ + if (omap2_i2c_active()) + return; - /* Jump to SRAM suspend code - * REVISIT: When is this SDRC_DLLB_CTRL? + /* The peripherals seem not to be able to wake up the MPU when + * it is in retention mode. */ + if (omap2_allow_mpu_retention()) { + /* REVISIT: These write to reserved bits? */ + prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + + /* Try to enter MPU retention */ + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + } else { + /* Block MPU retention */ + + prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); + only_idle = 1; + } + + if (omap2_pm_debug) { + omap2_pm_dump(only_idle ? 2 : 1, 0, 0); + sleep_time = omap2_read_32k_sync_counter(); + } + + omap2_sram_idle(); + + if (omap2_pm_debug) { + unsigned long long tmp; + u32 resume_time; + + resume_time = omap2_read_32k_sync_counter(); + tmp = resume_time - sleep_time; + tmp *= 1000000; + omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768); + } +} + +static int omap2_can_sleep(void) +{ + if (!enable_dyn_sleep) + return 0; + if (omap2_fclks_active()) + return 0; + if (atomic_read(&sleep_block) > 0) + return 0; + if (clk_get_usecount(osc_ck) > 1) + return 0; + if (omap_dma_running()) + return 0; + + return 1; +} + +static void omap2_pm_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + + if (!omap2_can_sleep()) { + /* timer_dyn_reprogram() takes about 100-200 us to complete. + * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA + * transfer to complete), the increased latency is too much. + * + * omap2_block_sleep() and omap2_allow_sleep() can be used + * to indicate this. + */ + if (atomic_read(&sleep_block) == 0) { + timer_dyn_reprogram(); + if (omap2_irq_pending()) + goto out; + } + omap2_enter_mpu_retention(); + goto out; + } + + /* + * Since an interrupt may set up a timer, we don't want to + * reprogram the hardware timer with interrupts enabled. + * Re-enable interrupts only after returning from idle. */ - omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type); + timer_dyn_reprogram(); + + if (omap2_irq_pending()) + goto out; - /* Back from sleep */ - omap2_pm_restore_registers(); + omap2_enter_full_retention(); +out: local_fiq_enable(); local_irq_enable(); +} + +static int omap2_pm_prepare(void) +{ + /* We cannot sleep in idle until we have resumed */ + saved_idle = pm_idle; + pm_idle = NULL; + + return 0; +} + +static int omap2_pm_suspend(void) +{ + u32 wken_wkup, mir1; + + wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); + prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); + + /* Mask GPT1 */ + mir1 = omap_readl(0x480fe0a4); + omap_writel(1 << 5, 0x480fe0ac); + + omap2_enter_full_retention(); + + omap_writel(mir1, 0x480fe0a4); + prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); return 0; } @@ -343,8 +619,7 @@ static int omap2_pm_enter(suspend_state_t state) { int ret = 0; - switch (state) - { + switch (state) { case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: ret = omap2_pm_suspend(); @@ -356,29 +631,181 @@ static int omap2_pm_enter(suspend_state_t state) return ret; } -static int omap2_pm_finish(suspend_state_t state) +static void omap2_pm_finish(void) { pm_idle = saved_idle; - return 0; } -static struct pm_ops omap_pm_ops = { +static struct platform_suspend_ops omap_pm_ops = { .prepare = omap2_pm_prepare, .enter = omap2_pm_enter, .finish = omap2_pm_finish, - .valid = pm_valid_only_mem, + .valid = suspend_valid_only_mem, }; +static void __init prcm_setup_regs(void) +{ + u32 l; + + /* Enable autoidle */ + __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG); + + /* Set all domain wakeup dependencies */ + prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP); + prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); + prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); + prm_write_mod_reg(0, CORE_MOD, PM_WKDEP); + if (cpu_is_omap2430()) + prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP); + + l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL); + /* Enable retention for all memory blocks */ + l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE | + OMAP24XX_MEM1RETSTATE; + + /* Set power state to RETENTION */ + l &= ~OMAP_POWERSTATE_MASK; + l |= 0x01 << OMAP_POWERSTATE_SHIFT; + prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL); + + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + + /* Power down DSP and GFX */ + prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT), + OMAP24XX_DSP_MOD, PM_PWSTCTRL); + prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT), + GFX_MOD, PM_PWSTCTRL); + + /* Enable clock auto control for all domains */ + cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 | + OMAP24XX_AUTOSTATE_L3, + CORE_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP, + OMAP24XX_DSP_MOD, CM_CLKSTCTRL); + + /* Enable clock autoidle for all domains */ + cm_write_mod_reg(OMAP24XX_AUTO_CAM | + OMAP24XX_AUTO_MAILBOXES | + OMAP24XX_AUTO_WDT4 | + OMAP2420_AUTO_WDT3 | + OMAP24XX_AUTO_MSPRO | + OMAP2420_AUTO_MMC | + OMAP24XX_AUTO_FAC | + OMAP2420_AUTO_EAC | + OMAP24XX_AUTO_HDQ | + OMAP24XX_AUTO_UART2 | + OMAP24XX_AUTO_UART1 | + OMAP24XX_AUTO_I2C2 | + OMAP24XX_AUTO_I2C1 | + OMAP24XX_AUTO_MCSPI2 | + OMAP24XX_AUTO_MCSPI1 | + OMAP24XX_AUTO_MCBSP2 | + OMAP24XX_AUTO_MCBSP1 | + OMAP24XX_AUTO_GPT12 | + OMAP24XX_AUTO_GPT11 | + OMAP24XX_AUTO_GPT10 | + OMAP24XX_AUTO_GPT9 | + OMAP24XX_AUTO_GPT8 | + OMAP24XX_AUTO_GPT7 | + OMAP24XX_AUTO_GPT6 | + OMAP24XX_AUTO_GPT5 | + OMAP24XX_AUTO_GPT4 | + OMAP24XX_AUTO_GPT3 | + OMAP24XX_AUTO_GPT2 | + OMAP2420_AUTO_VLYNQ | + OMAP24XX_AUTO_DSS, + CORE_MOD, CM_AUTOIDLE1); + cm_write_mod_reg(OMAP24XX_AUTO_UART3 | + OMAP24XX_AUTO_SSI | + OMAP24XX_AUTO_USB, + CORE_MOD, CM_AUTOIDLE2); + cm_write_mod_reg(OMAP24XX_AUTO_SDRC | + OMAP24XX_AUTO_GPMC | + OMAP24XX_AUTO_SDMA, + CORE_MOD, CM_AUTOIDLE3); + cm_write_mod_reg(OMAP24XX_AUTO_PKA | + OMAP24XX_AUTO_AES | + OMAP24XX_AUTO_RNG | + OMAP24XX_AUTO_SHA | + OMAP24XX_AUTO_DES, + CORE_MOD, OMAP24XX_CM_AUTOIDLE4); + + cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); + + /* Put DPLL and both APLLs into autoidle mode */ + cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | + (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT), + PLL_MOD, CM_AUTOIDLE); + + cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | + OMAP24XX_AUTO_WDT1 | + OMAP24XX_AUTO_MPU_WDT | + OMAP24XX_AUTO_GPIOS | + OMAP24XX_AUTO_32KSYNC | + OMAP24XX_AUTO_GPT1, + WKUP_MOD, CM_AUTOIDLE); + + /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk + * stabilisation */ + __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP); + + /* Configure automatic voltage transition */ + __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); + __raw_writel(OMAP24XX_AUTO_EXTVOLT | + (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | + OMAP24XX_MEMRETCTRL | + (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | + (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), + OMAP24XX_PRCM_VOLTCTRL); + + /* Enable wake-up events */ + prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, + WKUP_MOD, PM_WKEN); +} + int __init omap2_pm_init(void) { - printk("Power Management for TI OMAP.\n"); + u32 l; + int error; + + printk(KERN_INFO "Power Management for OMAP2 initializing\n"); + l = __raw_readl(OMAP24XX_PRCM_REVISION); + printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - vclk = clk_get(NULL, "virt_prcm_set"); - if (IS_ERR(vclk)) { - printk(KERN_ERR "Could not get PM vclk\n"); + osc_ck = clk_get(NULL, "osc_ck"); + if (IS_ERR(osc_ck)) { + printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } + if (cpu_is_omap242x()) { + emul_ck = clk_get(NULL, "emul_ck"); + if (IS_ERR(emul_ck)) { + printk(KERN_ERR "could not get emul_ck\n"); + clk_put(osc_ck); + return -ENODEV; + } + } + + prcm_setup_regs(); + + pm_init_serial_console(); + + /* Hack to prevent MPU retention when STI console is enabled. */ + { + const struct omap_sti_console_config *sti; + + sti = omap_get_config(OMAP_TAG_STI_CONSOLE, + struct omap_sti_console_config); + if (sti != NULL && sti->enable) + sti_console_enabled = 1; + } + /* * We copy the assembler sleep/wakeup routines to SRAM. * These routines need to be in SRAM as that's the only @@ -390,12 +817,22 @@ int __init omap2_pm_init(void) omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, omap24xx_cpu_suspend_sz); - pm_set_ops(&omap_pm_ops); + /* Patch in the correct register addresses for multiboot */ + omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power, + omap2_sram_suspend, + OMAP_SDRC_REGADDR(SDRC_POWER)); + omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl, + omap2_sram_suspend, + OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); + + suspend_set_ops(&omap_pm_ops); pm_idle = omap2_pm_idle; - pmdomain_init(); + error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); + if (error) + printk(KERN_ERR "sysfs_create_file failed: %d\n", error); return 0; } -__initcall(omap2_pm_init); +late_initcall(omap2_pm_init);