X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Fblackfin%2Fkernel%2Freboot.c;h=367e2dc0988195a9ed6d41e5acda35a00cc088f4;hb=9dfda12b8b769e224ca4efbc35ace4524b9c017b;hp=483f93dfc1b590a7ea6cdc582a40eadd3d17982e;hpb=8561b089afbaed2651591e5a4574fdca451d82f2;p=linux-2.6-omap-h63xx.git

diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 483f93dfc1b..367e2dc0988 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -11,45 +11,56 @@
 #include <asm/reboot.h>
 #include <asm/system.h>
 
-#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY)
-#define SYSCR_VAL 	0x0
-#elif defined(BF561_FAMILY)
-#define SYSCR_VAL 	0x20
-#elif defined(BF548_FAMILY)
-#define SYSCR_VAL 	0x10
-#endif
-
-/*
- * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
- */
-#define SWRST_DELAY	(5 * 15)
-
-/* A system soft reset makes external memory unusable
- * so force this function into L1.
+/* A system soft reset makes external memory unusable so force
+ * this function into L1.  We use the compiler ssync here rather
+ * than SSYNC() because it's safe (no interrupts and such) and
+ * we save some L1.  We do not need to force sanity in the SYSCR
+ * register as the BMODE selection bit is cleared by the soft
+ * reset while the Core B bit (on dual core parts) is cleared by
+ * the core reset.
  */
 __attribute__((l1_text))
 void bfin_reset(void)
 {
-	/* force BMODE and disable Core B (as needed) */
-	bfin_write_SYSCR(SYSCR_VAL);
-
-	/* we use asm ssync here because it's save and we save some L1 */
-	asm("ssync;");
+	/* Wait for completion of "system" events such as cache line
+	 * line fills so that we avoid infinite stalls later on as
+	 * much as possible.  This code is in L1, so it won't trigger
+	 * any such event after this point in time.
+	 */
+	__builtin_bfin_ssync();
 
 	while (1) {
-		/* initiate system soft reset with magic 0x7 */
+		/* Initiate System software reset. */
 		bfin_write_SWRST(0x7);
 
-		/* Wait for System reset to actually reset, needs to be 5 SCLKs, */
-		/* Assume CCLK / SCLK ratio is worst case (15), and use 5*15     */
-
-		asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n"
-		 : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
+		/* Due to the way reset is handled in the hardware, we need
+		 * to delay for 7 SCLKS.  The only reliable way to do this is
+		 * to calculate the CCLK/SCLK ratio and multiply 7.  For now,
+		 * we'll assume worse case which is a 1:15 ratio.
+		 */
+		asm(
+			"LSETUP (1f, 1f) LC0 = %0\n"
+			"1: nop;"
+			:
+			: "a" (15 * 7)
+			: "LC0", "LB0", "LT0"
+		);
 
-		/* clear system soft reset */
+		/* Clear System software reset */
 		bfin_write_SWRST(0);
-		asm("ssync;");
-		/* issue core reset */
+
+		/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+		 * though as the System state is all reset now.
+		 */
+		asm(
+			"LSETUP (1f, 1f) LC1 = %0\n"
+			"1: nop;"
+			:
+			: "a" (15 * 1)
+			: "LC1", "LB1", "LT1"
+		);
+
+		/* Issue core reset */
 		asm("raise 1");
 	}
 }