X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Fs390%2Fkernel%2Freipl.S;h=2f481cc3d1c9c13bc5db45ad4987f51e4a07e9a5;hb=2254c2e0184c603f92fc9b81016ff4bb53da622d;hp=f9434d42ce9f60f65ec2b57d84684b4d82677300;hpb=c4366889dda8110247be59ca41fddb82951a8c26;p=linux-2.6-omap-h63xx.git diff --git a/arch/s390/kernel/reipl.S b/arch/s390/kernel/reipl.S index f9434d42ce9..2f481cc3d1c 100644 --- a/arch/s390/kernel/reipl.S +++ b/arch/s390/kernel/reipl.S @@ -8,6 +8,10 @@ #include +# +# do_reipl_asm +# Parameter: r2 = schid of reipl device +# .globl do_reipl_asm do_reipl_asm: basr %r13,0 .Lpg0: lpsw .Lnewpsw-.Lpg0(%r13) @@ -16,12 +20,12 @@ do_reipl_asm: basr %r13,0 stm %r0,%r15,__LC_GPREGS_SAVE_AREA stctl %c0,%c15,__LC_CREGS_SAVE_AREA stam %a0,%a15,__LC_AREGS_SAVE_AREA - stpx __LC_PREFIX_SAVE_AREA + l %r10,.Ldump_pfx-.Lpg0(%r13) + mvc __LC_PREFIX_SAVE_AREA(4),0(%r10) stckc .Lclkcmp-.Lpg0(%r13) mvc __LC_CLOCK_COMP_SAVE_AREA(8),.Lclkcmp-.Lpg0(%r13) stpt __LC_CPU_TIMER_SAVE_AREA st %r13, __LC_PSW_SAVE_AREA+4 - lctl %c6,%c6,.Lall-.Lpg0(%r13) lr %r1,%r2 mvc __LC_PGM_NEW_PSW(8),.Lpcnew-.Lpg0(%r13) @@ -55,6 +59,7 @@ do_reipl_asm: basr %r13,0 .align 8 .Lclkcmp: .quad 0x0000000000000000 .Lall: .long 0xff000000 +.Ldump_pfx: .long dump_prefix_page .align 8 .Lnewpsw: .long 0x00080000,0x80000000+.Lpg1 .Lpcnew: .long 0x00080000,0x80000000+.Lecs