X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fnatsemi.c;h=46119bb3770a65b19e1dc21c5301e1e2358bf879;hb=577b4a58d2e74a4d48050eeea3e3f952ce04eb86;hp=c329a4f5840c7c22ee80a2882343888ea13ffbde;hpb=9ea7d6cb9c223e8b0887b8b0355470acb947a1c9;p=linux-2.6-omap-h63xx.git diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index c329a4f5840..46119bb3770 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -127,7 +127,7 @@ static int full_duplex[MAX_UNITS]; #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ /* These identify the driver base version and may not be removed. */ -static const char version[] __devinitdata = +static char version[] __devinitdata = KERN_INFO DRV_NAME " dp8381x driver, version " DRV_VERSION ", " DRV_RELDATE "\n" KERN_INFO " originally by Donald Becker \n" @@ -203,22 +203,8 @@ skbuff at an offset of "+2", 16-byte aligning the IP header. IIId. Synchronization Most operations are synchronized on the np->lock irq spinlock, except the -performance critical codepaths: - -The rx process only runs in the interrupt handler. Access from outside -the interrupt handler is only permitted after disable_irq(). - -The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap -is set, then access is permitted under spin_lock_irq(&np->lock). - -Thus configuration functions that want to access everything must call - disable_irq(dev->irq); - netif_tx_lock_bh(dev); - spin_lock_irq(&np->lock); - -IV. Notes - -NatSemi PCI network controllers are very uncommon. +recieve and transmit paths which are synchronised using a combination of +hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. IVb. References @@ -252,7 +238,7 @@ enum { }; /* array of board data directly indexed by pci_tbl[x].driver_data */ -static const struct { +static struct { const char *name; unsigned long flags; unsigned int eeprom_size; @@ -261,7 +247,7 @@ static const struct { { "NatSemi DP8381[56]", 0, 24 }, }; -static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = { +static struct pci_device_id natsemi_pci_tbl[] __devinitdata = { { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 }, { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, { } /* terminate list */ @@ -525,10 +511,10 @@ enum PhyCtrl_bits { /* Note that using only 32 bit fields simplifies conversion to big-endian architectures. */ struct netdev_desc { - u32 next_desc; - s32 cmd_status; - u32 addr; - u32 software_use; + __le32 next_desc; + __le32 cmd_status; + __le32 addr; + __le32 software_use; }; /* Bits in network_desc.status */ @@ -800,7 +786,8 @@ static int __devinit natsemi_probe1 (struct pci_dev *pdev, struct netdev_private *np; int i, option, irq, chip_idx = ent->driver_data; static int find_cnt = -1; - unsigned long iostart, iosize; + resource_size_t iostart; + unsigned long iosize; void __iomem *ioaddr; const int pcibar = 1; /* PCI base address register */ int prev_eedata; @@ -960,10 +947,11 @@ static int __devinit natsemi_probe1 (struct pci_dev *pdev, goto err_create_file; if (netif_msg_drv(np)) { - printk(KERN_INFO "natsemi %s: %s at %#08lx " + printk(KERN_INFO "natsemi %s: %s at %#08llx " "(%s), %s, IRQ %d", - dev->name, natsemi_pci_info[chip_idx].name, iostart, - pci_name(np->pci_dev), print_mac(mac, dev->dev_addr), irq); + dev->name, natsemi_pci_info[chip_idx].name, + (unsigned long long)iostart, pci_name(np->pci_dev), + print_mac(mac, dev->dev_addr), irq); if (dev->if_port == PORT_TP) printk(", port TP.\n"); else if (np->ignore_phy) @@ -2032,7 +2020,7 @@ static void drain_rx(struct net_device *dev) /* Free all the skbuffs in the Rx queue. */ for (i = 0; i < RX_RING_SIZE; i++) { np->rx_ring[i].cmd_status = 0; - np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */ + np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ if (np->rx_skbuff[i]) { pci_unmap_single(np->pci_dev, np->rx_dma[i], buflen,