X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fqla3xxx.h;h=58a086fddec69f1e88407dada260eab2ca11ef72;hb=7fc077fba5f8896c6fed3b35c5a10e7fdae82bbe;hp=0203f88f0544413eb52c6a30c5c70797435aff92;hpb=14d21785885c018611efd8aa75a5c11eaea29087;p=linux-2.6-omap-h63xx.git diff --git a/drivers/net/qla3xxx.h b/drivers/net/qla3xxx.h old mode 100755 new mode 100644 index 0203f88f054..58a086fddec --- a/drivers/net/qla3xxx.h +++ b/drivers/net/qla3xxx.h @@ -50,7 +50,7 @@ struct ob_mac_iocb_req { #define OB_3032MAC_IOCB_REQ_UC 0x01 u8 reserved0; - __le32 transaction_id; + u32 transaction_id; /* opaque for hardware */ __le16 data_len; u8 ip_hdr_off; u8 ip_hdr_len; @@ -86,7 +86,7 @@ struct ob_mac_iocb_rsp { #define OB_MAC_IOCB_RSP_I 0x01 __le16 reserved0; - __le32 transaction_id; + u32 transaction_id; /* opaque for hardware */ __le32 reserved1; __le32 reserved2; }; @@ -293,6 +293,16 @@ struct net_rsp_iocb { #define MII_SCAN_REGISTER 0x00000001 +#define PHY_ID_0_REG 2 +#define PHY_ID_1_REG 3 + +#define PHY_OUI_1_MASK 0xfc00 +#define PHY_MODEL_MASK 0x03f0 + +/* Address for the Agere Phy */ +#define MII_AGERE_ADDR_1 0x00001000 +#define MII_AGERE_ADDR_2 0x00001100 + /* 32-bit ispControlStatus */ enum { ISP_CONTROL_NP_MASK = 0x0003, @@ -546,7 +556,7 @@ enum { IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007, IP_ADDR_INDEX_REG_6 = 0x0008, IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030, - IP_ADDR_INDEX_REG_E = 0x0040, + IP_ADDR_INDEX_REG_E = 0x0040, }; enum { QL3032_PORT_CONTROL_DS = 0x0001, @@ -789,6 +799,7 @@ enum { PHY_CTRL_LOOPBACK = 0x4000, PETBI_CONTROL_REG = 0x00, + PETBI_CTRL_ALL_PARAMS = 0x7140, PETBI_CTRL_SOFT_RESET = 0x8000, PETBI_CTRL_AUTO_NEG = 0x1000, PETBI_CTRL_RESTART_NEG = 0x0200, @@ -811,6 +822,23 @@ enum { PETBI_EXPANSION_REG = 0x06, PETBI_EXP_PAGE_RX = 0x0002, + PHY_GIG_CONTROL = 9, + PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/ + PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/ + PHY_GIG_ALL_PARAMS = 0x0300, + PHY_GIG_ADV_1000F = 0x0200, + PHY_GIG_ADV_1000H = 0x0100, + + PHY_NEG_ADVER = 4, + PHY_NEG_ALL_PARAMS = 0x0fe0, + PHY_NEG_ASY_PAUSE = 0x0800, + PHY_NEG_SYM_PAUSE = 0x0400, + PHY_NEG_ADV_SPEED = 0x01e0, + PHY_NEG_ADV_100F = 0x0100, + PHY_NEG_ADV_100H = 0x0080, + PHY_NEG_ADV_10F = 0x0040, + PHY_NEG_ADV_10H = 0x0020, + PETBI_TBI_CTRL = 0x11, PETBI_TBI_RESET = 0x8000, PETBI_TBI_AUTO_SENSE = 0x0100, @@ -826,8 +854,7 @@ enum { PHY_AUX_RESET_STICK = 0x0002, PHY_NEG_PAUSE = 0x0400, PHY_CTRL_SOFT_RESET = 0x8000, - PHY_NEG_ADVER = 4, - PHY_NEG_ADV_SPEED = 0x01e0, + PHY_CTRL_AUTO_NEG = 0x1000, PHY_CTRL_RESTART_NEG = 0x0200, }; enum { @@ -892,6 +919,7 @@ enum {EEPROM_SIZE = FM93C86A_SIZE_16, u16 pauseThreshold_mac; u16 resumeThreshold_mac; u16 portConfiguration; +#define PORT_CONFIG_DEFAULT 0xf700 #define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000 #define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000 #define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000 @@ -925,8 +953,8 @@ struct eeprom_bios_cfg { */ struct eeprom_function_cfg { u8 reserved[30]; - u8 macAddress[6]; - u8 macAddressSecondary[6]; + u16 macAddress[3]; + u16 macAddressSecondary[3]; u16 subsysVendorId; u16 subsysDeviceId; @@ -937,8 +965,7 @@ struct eeprom_function_cfg { */ struct eeprom_data { u8 asicId[4]; - u8 version; - u8 numPorts; + u16 version_and_numPorts; /* together to avoid endianness crap */ u16 boardId; #define EEPROM_BOARDID_STR_SIZE 16 @@ -1028,31 +1055,31 @@ struct eeprom_data { */ struct lrg_buf_q_entry { - u32 addr0_lower; + __le32 addr0_lower; #define IAL_LAST_ENTRY 0x00000001 #define IAL_CONT_ENTRY 0x00000002 #define IAL_FLAG_MASK 0x00000003 - u32 addr0_upper; - u32 addr1_lower; - u32 addr1_upper; - u32 addr2_lower; - u32 addr2_upper; - u32 addr3_lower; - u32 addr3_upper; - u32 addr4_lower; - u32 addr4_upper; - u32 addr5_lower; - u32 addr5_upper; - u32 addr6_lower; - u32 addr6_upper; - u32 addr7_lower; - u32 addr7_upper; + __le32 addr0_upper; + __le32 addr1_lower; + __le32 addr1_upper; + __le32 addr2_lower; + __le32 addr2_upper; + __le32 addr3_lower; + __le32 addr3_upper; + __le32 addr4_lower; + __le32 addr4_upper; + __le32 addr5_lower; + __le32 addr5_upper; + __le32 addr6_lower; + __le32 addr6_upper; + __le32 addr7_lower; + __le32 addr7_upper; }; struct bufq_addr_element { - u32 addr_low; - u32 addr_high; + __le32 addr_low; + __le32 addr_high; }; #define QL_NO_RESET 0 @@ -1084,13 +1111,13 @@ struct ql_rcv_buf_cb { * OAL has 5 entries: * 1 thru 4 point to frags * fifth points to next oal. - */ + */ #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1) struct oal_entry { - u32 dma_lo; - u32 dma_hi; - u32 len; + __le32 dma_lo; + __le32 dma_hi; + __le32 len; #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */ #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */ }; @@ -1109,7 +1136,7 @@ struct ql_tx_buf_cb { struct ob_mac_iocb_req *queue_entry ; int seg_count; struct oal *oal; - struct map_list map[MAX_SKB_FRAGS+1]; + struct map_list map[MAX_SKB_FRAGS+1]; }; /* definitions for type field */ @@ -1147,6 +1174,8 @@ struct ql3_adapter { struct pci_dev *pdev; struct net_device *ndev; /* Parent NET device */ + struct napi_struct napi; + /* Hardware information */ u8 chip_rev_id; u8 pci_slot; @@ -1193,7 +1222,7 @@ struct ql3_adapter { struct net_rsp_iocb *rsp_current; u16 rsp_consumer_index; u16 reserved_06; - volatile u32 *prsp_producer_index; + volatile __le32 *prsp_producer_index; u32 rsp_producer_index_phy_addr_high; u32 rsp_producer_index_phy_addr_low; @@ -1253,12 +1282,13 @@ struct ql3_adapter { u32 update_ob_opcode; /* Opcode to use for updating NCB */ u32 mb_bit_mask; /* MA Bits mask to use on transmission */ u32 numPorts; - struct net_device_stats stats; struct workqueue_struct *workqueue; struct delayed_work reset_work; struct delayed_work tx_timeout_work; + struct delayed_work link_state_work; u32 max_frame_size; u32 device_id; + u16 phyType; }; #endif /* _QLA3XXX_H_ */