X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fsky2.h;h=95518921001c47d03789ae15729234c72ecbf733;hb=0271fc2db6260dd46f196191e24281af2fddb879;hp=b1acdc606f3138e25c1b8f3ac8bb042a069d2dd4;hpb=90890687859ea658759e653c4e70ed7e9e1a6217;p=linux-2.6-omap-h63xx.git diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index b1acdc606f3..95518921001 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -85,21 +85,6 @@ enum csr_regs { B0_IMSK = 0x000c, B0_HWE_ISRC = 0x0010, B0_HWE_IMSK = 0x0014, - B0_SP_ISRC = 0x0018, - B0_XM1_IMSK = 0x0020, - B0_XM1_ISRC = 0x0028, - B0_XM1_PHY_ADDR = 0x0030, - B0_XM1_PHY_DATA = 0x0034, - B0_XM2_IMSK = 0x0040, - B0_XM2_ISRC = 0x0048, - B0_XM2_PHY_ADDR = 0x0050, - B0_XM2_PHY_DATA = 0x0054, - B0_R1_CSR = 0x0060, - B0_R2_CSR = 0x0064, - B0_XS1_CSR = 0x0068, - B0_XA1_CSR = 0x006c, - B0_XS2_CSR = 0x0070, - B0_XA2_CSR = 0x0074, /* Special ISR registers (Yukon-2 only) */ B0_Y2_SP_ISRC2 = 0x001c, @@ -116,36 +101,25 @@ enum csr_regs { B2_MAC_CFG = 0x011a, B2_CHIP_ID = 0x011b, B2_E_0 = 0x011c, - B2_E_1 = 0x011d, - B2_E_2 = 0x011e, + B2_Y2_CLK_GATE = 0x011d, B2_Y2_HW_RES = 0x011e, B2_E_3 = 0x011f, B2_Y2_CLK_CTRL = 0x0120, - B2_LD_CTRL = 0x0128, - B2_LD_TEST = 0x0129, + B2_TI_INI = 0x0130, B2_TI_VAL = 0x0134, B2_TI_CTRL = 0x0138, B2_TI_TEST = 0x0139, - B2_IRQM_INI = 0x0140, - B2_IRQM_VAL = 0x0144, - B2_IRQM_CTRL = 0x0148, - B2_IRQM_TEST = 0x0149, - B2_IRQM_MSK = 0x014c, - B2_IRQM_HWE_MSK = 0x0150, + B2_TST_CTRL1 = 0x0158, B2_TST_CTRL2 = 0x0159, B2_GP_IO = 0x015c, + B2_I2C_CTRL = 0x0160, B2_I2C_DATA = 0x0164, B2_I2C_IRQ = 0x0168, B2_I2C_SW = 0x016c, - B2_BSC_INI = 0x0170, - B2_BSC_VAL = 0x0174, - B2_BSC_CTRL = 0x0178, - B2_BSC_STAT = 0x0179, - B2_BSC_TST = 0x017a, B3_RAM_ADDR = 0x0180, B3_RAM_DATA_LO = 0x0184, @@ -220,8 +194,6 @@ enum { Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ - CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */ - CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */ CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ CS_STOP_DONE = 1<<5, /* Stop Master is finished */ @@ -337,7 +309,7 @@ enum { Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | - Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP | + Y2_IS_PCI_EXP | Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, }; @@ -374,6 +346,7 @@ enum { CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */ CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */ CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ + CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ @@ -384,11 +357,11 @@ enum { /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ enum { - Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */ + Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ - Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */ + Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ @@ -438,7 +411,7 @@ enum { #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ /* RAM Interface Registers */ -/* B3_RI_CTRL 16 bit RAM Iface Control Register */ +/* B3_RI_CTRL 16 bit RAM Interface Control Register */ enum { RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ @@ -607,7 +580,8 @@ enum { RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ - + RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ + RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ @@ -641,7 +615,7 @@ enum { BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ - BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */ + BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ BMU_START = 1<<8, /* Start Rx/Tx Queue */ @@ -657,6 +631,8 @@ enum { BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | BMU_FIFO_ENA | BMU_OP_ON, + + BMU_WM_DEFAULT = 0x600, }; /* Tx BMU Control / Status Registers (Yukon-2) */ @@ -664,7 +640,7 @@ enum { enum { BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ - BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */ + BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ }; /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ @@ -1585,6 +1561,9 @@ enum { /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ enum { + TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ + TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ + TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ @@ -1769,40 +1748,44 @@ enum { */ struct sky2_tx_le { union { - u32 addr; + __le32 addr; struct { - u16 offset; - u16 start; + __le16 offset; + __le16 start; } csum __attribute((packed)); struct { - u16 size; - u16 rsvd; + __le16 size; + __le16 rsvd; } tso __attribute((packed)); } tx; - u16 length; /* also vlan tag or checksum start */ + __le16 length; /* also vlan tag or checksum start */ u8 ctrl; u8 opcode; } __attribute((packed)); struct sky2_rx_le { - u32 addr; - u16 length; + __le32 addr; + __le16 length; u8 ctrl; u8 opcode; } __attribute((packed));; struct sky2_status_le { - u32 status; /* also checksum */ - u16 length; /* also vlan tag */ + __le32 status; /* also checksum */ + __le16 length; /* also vlan tag */ u8 link; u8 opcode; } __attribute((packed)); +struct tx_ring_info { + struct sk_buff *skb; + DECLARE_PCI_UNMAP_ADDR(mapaddr); + u16 idx; +}; + struct ring_info { struct sk_buff *skb; dma_addr_t mapaddr; - u16 maplen; - u16 idx; }; struct sky2_port { @@ -1811,23 +1794,24 @@ struct sky2_port { unsigned port; u32 msg_enable; - struct ring_info *tx_ring; + spinlock_t tx_lock ____cacheline_aligned_in_smp; + struct tx_ring_info *tx_ring; struct sky2_tx_le *tx_le; - spinlock_t tx_lock; - u32 tx_addr64; u16 tx_cons; /* next le to check */ u16 tx_prod; /* next le to use */ + u32 tx_addr64; u16 tx_pending; u16 tx_last_put; u16 tx_last_mss; - struct ring_info *rx_ring; + struct ring_info *rx_ring ____cacheline_aligned_in_smp; struct sky2_rx_le *rx_le; u32 rx_addr64; u16 rx_next; /* next re to check */ u16 rx_put; /* next le index to use */ u16 rx_pending; u16 rx_last_put; + u16 rx_bufsize; #ifdef SKY2_VLAN_TAG_USED u16 rx_tag; struct vlan_group *vlgrp; @@ -1844,8 +1828,10 @@ struct sky2_port { u8 rx_csum; u8 wol; - struct tasklet_struct phy_task; struct net_device_stats net_stats; + + struct work_struct phy_task; + struct semaphore phy_sema; }; struct sky2_hw { @@ -1863,8 +1849,6 @@ struct sky2_hw { struct sky2_status_le *st_le; u32 st_idx; dma_addr_t st_dma; - - spinlock_t phy_lock; }; /* Register accessor for memory mapped device */