X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fscsi%2Fqla2xxx%2Fqla_dbg.c;h=2d9b12ffe09c3b9f85ecdd2d2f03d19dc91aa2d7;hb=1f84253e3ce75fc1b2946a544e16c5c0c13c7017;hp=9791496fa78844076de8192e5a907013312715ee;hpb=486a153f0e294f7cc735838edcb6b32e623cbe52;p=linux-2.6-omap-h63xx.git diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 9791496fa78..2d9b12ffe09 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -1,20 +1,8 @@ /* - * QLOGIC LINUX SOFTWARE - * - * QLogic ISP2x00 device driver for Linux 2.6.x - * Copyright (C) 2003-2005 QLogic Corporation - * (www.qlogic.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2, or (at your option) any - * later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. + * QLogic Fibre Channel HBA Driver + * Copyright (c) 2003-2005 QLogic Corporation * + * See LICENSE.qla2xxx for copyright and licensing details. */ #include "qla_def.h" @@ -982,7 +970,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) int rval; uint32_t cnt, timer; uint32_t risc_address; - uint16_t mb[4]; + uint16_t mb[4], wd; uint32_t stat; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; @@ -1015,10 +1003,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) fw = (struct qla24xx_fw_dump *) ha->fw_dump24; rval = QLA_SUCCESS; - fw->hccr = RD_REG_DWORD(®->hccr); + fw->host_status = RD_REG_DWORD(®->host_status); /* Pause RISC. */ - if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) { + if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | HCCRX_CLR_HOST_INT); RD_REG_DWORD(®->hccr); /* PCI Posting. */ @@ -1033,16 +1021,54 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) } } - /* Disable interrupts. */ - WRT_REG_DWORD(®->ictrl, 0); - RD_REG_DWORD(®->ictrl); - if (rval == QLA_SUCCESS) { /* Host interface registers. */ dmp_reg = (uint32_t __iomem *)(reg + 0); for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); + /* Disable interrupts. */ + WRT_REG_DWORD(®->ictrl, 0); + RD_REG_DWORD(®->ictrl); + + /* Shadow registers. */ + WRT_REG_DWORD(®->iobase_addr, 0x0F70); + RD_REG_DWORD(®->iobase_addr); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0000000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0100000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0200000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0300000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0400000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0500000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0600000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); + /* Mailbox registers. */ mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) @@ -1320,43 +1346,6 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = RD_REG_DWORD(dmp_reg++); - WRT_REG_DWORD(®->iobase_addr, 0x0F70); - RD_REG_DWORD(®->iobase_addr); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0000000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0100000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0200000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0300000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0400000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0500000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0600000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); - /* Local memory controller registers. */ iter_reg = fw->lmc_reg; WRT_REG_DWORD(®->iobase_addr, 0x3000); @@ -1526,10 +1515,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); - RD_REG_DWORD(®->ctrl_status); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + udelay(100); /* Wait for firmware to complete NVRAM accesses. */ - udelay(5); mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); for (cnt = 10000 ; cnt && mb[0]; cnt--) { udelay(5); @@ -1537,7 +1526,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) barrier(); } - udelay(20); + /* Wait for soft-reset to complete. */ for (cnt = 0; cnt < 30000; cnt++) { if ((RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET) == 0) @@ -1689,7 +1678,7 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha) ha->fw_major_version, ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); - qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr); + qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status); qla_uprintf(&uiter, "\nHost Interface Registers"); for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) { @@ -1699,6 +1688,14 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha) qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]); } + qla_uprintf(&uiter, "\n\nShadow Registers"); + for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) { + if (cnt % 8 == 0) + qla_uprintf(&uiter, "\n"); + + qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]); + } + qla_uprintf(&uiter, "\n\nMailbox Registers"); for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) { if (cnt % 8 == 0) @@ -1867,14 +1864,6 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha) qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]); } - qla_uprintf(&uiter, "\n\nShadow Registers"); - for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) { - if (cnt % 8 == 0) - qla_uprintf(&uiter, "\n"); - - qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]); - } - qla_uprintf(&uiter, "\n\nLMC Registers"); for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) { if (cnt % 8 == 0)