X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fserial%2Fatmel_serial.c;h=3320bcd92c0a3b54de5b3da4c52a9c1683bb84eb;hb=03abeac0a222060ae8f02e8359c285df0971437e;hp=ed7f7209ea5926a8aa840b667884448f6c232ead;hpb=cece901481bafbf14de8cbd3a89ae869ea881055;p=linux-2.6-omap-h63xx.git diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index ed7f7209ea5..3320bcd92c0 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c @@ -33,12 +33,13 @@ #include #include #include +#include #include #include #include -#include + #ifdef CONFIG_ARM #include #include @@ -73,35 +74,35 @@ #define ATMEL_ISR_PASS_LIMIT 256 -#define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR) -#define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR) -#define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR) -#define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER) -#define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR) -#define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR) -#define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR) -#define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR) -#define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR) -#define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR) -#define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR) -#define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR) - -// #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only +#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) +#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) +#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) +#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) +#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) +#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) +#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) +#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) +#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) +#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) +#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) +#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) + +// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only /* PDC registers */ -#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR) -#define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR) +#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) +#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) -#define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR) -#define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR) -#define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR) -#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR) -#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR) +#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) +#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) +#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) +#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) +#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) -#define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR) -#define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR) -//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR) -//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR) +#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) +#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) +//#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR) +//#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR) static int (*atmel_open_hook)(struct uart_port *); static void (*atmel_close_hook)(struct uart_port *); @@ -483,11 +484,16 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, unsigned long flags; unsigned int mode, imr, quot, baud; + /* Get current mode register */ + mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); quot = uart_get_divisor(port, baud); - /* Get current mode register */ - mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); + if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ + quot /= 8; + mode |= ATMEL_US_USCLKS_MCK_DIV8; + } /* byte size */ switch (termios->c_cflag & CSIZE) { @@ -689,9 +695,9 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct struct atmel_uart_data *data = pdev->dev.platform_data; port->iotype = UPIO_MEM; - port->flags = UPF_BOOT_AUTOCONF; + port->flags = UPF_BOOT_AUTOCONF; port->ops = &atmel_pops; - port->fifosize = 1; + port->fifosize = 1; port->line = pdev->id; port->dev = &pdev->dev; @@ -890,7 +896,6 @@ static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) enable_irq_wake(port->irq); else { - disable_irq_wake(port->irq); uart_suspend_port(&atmel_uart, port); atmel_port->suspended = 1; } @@ -907,6 +912,8 @@ static int atmel_serial_resume(struct platform_device *pdev) uart_resume_port(&atmel_uart, port); atmel_port->suspended = 0; } + else + disable_irq_wake(port->irq); return 0; }