X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-arm%2Flocks.h;h=852220eecdbc5d3147528bd6853f2a039ae91543;hb=6a8b23086c82d7cc4f424518532c8b10d95715c0;hp=9cb33fcc06c15e193086452b95c532085d52134e;hpb=6b6a93c6876ea1c530d5d3f68e3678093a27fab0;p=linux-2.6-omap-h63xx.git

diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index 9cb33fcc06c..852220eecdb 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -28,7 +28,8 @@
 "	blmi	" #fail				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	})
 
 #define __down_op_ret(ptr,fail)			\
@@ -48,12 +49,14 @@
 "	mov	%0, ip"				\
 	: "=&r" (ret)				\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	ret;					\
 	})
 
 #define __up_op(ptr,wake)			\
 	({					\
+	smp_mb();				\
 	__asm__ __volatile__(			\
 	"@ up_op\n"				\
 "1:	ldrex	lr, [%0]\n"			\
@@ -66,7 +69,7 @@
 "	blle	" #wake				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
 	})
 
 /*
@@ -92,13 +95,15 @@
 "	blne	" #fail				\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	})
 
 #define __up_op_write(ptr,wake)			\
 	({					\
+	smp_mb();				\
 	__asm__ __volatile__(			\
-	"@ up_op_read\n"			\
+	"@ up_op_write\n"			\
 "1:	ldrex	lr, [%0]\n"			\
 "	adds	lr, lr, %1\n"			\
 "	strex	ip, lr, [%0]\n"			\
@@ -108,7 +113,7 @@
 "	blcs	" #wake				\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
 	})
 
 #define __down_op_read(ptr,fail)		\
@@ -116,6 +121,7 @@
 
 #define __up_op_read(ptr,wake)			\
 	({					\
+	smp_mb();				\
 	__asm__ __volatile__(			\
 	"@ up_op_read\n"			\
 "1:	ldrex	lr, [%0]\n"			\
@@ -128,7 +134,7 @@
 "	bleq	" #wake				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
 	})
 
 #else
@@ -148,7 +154,8 @@
 "	blmi	" #fail				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	})
 
 #define __down_op_ret(ptr,fail)			\
@@ -169,12 +176,14 @@
 "	mov	%0, ip"				\
 	: "=&r" (ret)				\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	ret;					\
 	})
 
 #define __up_op(ptr,wake)			\
 	({					\
+	smp_mb();				\
 	__asm__ __volatile__(			\
 	"@ up_op\n"				\
 "	mrs	ip, cpsr\n"			\
@@ -188,7 +197,7 @@
 "	blle	" #wake				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
 	})
 
 /*
@@ -215,13 +224,14 @@
 "	blne	" #fail				\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	})
 
 #define __up_op_write(ptr,wake)			\
 	({					\
 	__asm__ __volatile__(			\
-	"@ up_op_read\n"			\
+	"@ up_op_write\n"			\
 "	mrs	ip, cpsr\n"			\
 "	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
@@ -233,7 +243,8 @@
 "	blcs	" #wake				\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
+	smp_mb();				\
 	})
 
 #define __down_op_read(ptr,fail)		\
@@ -241,6 +252,7 @@
 
 #define __up_op_read(ptr,wake)			\
 	({					\
+	smp_mb();				\
 	__asm__ __volatile__(			\
 	"@ up_op_read\n"			\
 "	mrs	ip, cpsr\n"			\
@@ -254,7 +266,7 @@
 "	bleq	" #wake				\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc", "memory");		\
+	: "ip", "lr", "cc");			\
 	})
 
 #endif