X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-m68knommu%2Fmcfcache.h;h=7b61a8a529f52063fa01b760a78ca125b4e3235a;hb=2eaff915744b6c8db7770fa9e841fd1c0105fb0b;hp=9cb4014218351515226443804a96e73768ac17a6;hpb=4f4ef2967e1e8dce43e9cf7186aeb60a8c33aaf4;p=linux-2.6-omap-h63xx.git

diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index 9cb40142183..7b61a8a529f 100644
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -11,7 +11,6 @@
 #define	__M68KNOMMU_MCFCACHE_H
 /****************************************************************************/
 
-#include <linux/config.h>
 
 /*
  *	The different ColdFire families have different cache arrangments.
@@ -93,6 +92,21 @@
 .endm
 #endif /* CONFIG_M5249 || CONFIG_M5307 */
 
+#if defined(CONFIG_M532x)
+.macro CACHE_ENABLE
+	movel	#0x01000000,%d0		/* invalidate cache cmd */
+	movec	%d0,%CACR		/* do invalidate cache */
+	nop
+	movel	#0x4001C000,%d0		/* set SDRAM cached (write-thru) */
+	movec	%d0,%ACR0
+	movel	#0x00000000,%d0		/* no other regions cached */
+	movec	%d0,%ACR1
+	movel	#0x80000200,%d0		/* setup cache mask */
+	movec	%d0,%CACR		/* enable cache */
+	nop
+.endm
+#endif /* CONFIG_M532x */
+
 #if defined(CONFIG_M5407)
 /*
  *	Version 4 cores have a true harvard style separate instruction