X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-mips%2Fcpu.h;h=818b9a97e214280c0c6a93af52699028e32a95bb;hb=34ca959cfc15cf09ad4da4f31ab034691e51af78;hp=46b2a8dc2ee0fc506e09edb5055c8692e3b87f51;hpb=02cf2119684e52e97a8a90bd7630386e0f1a250a;p=linux-2.6-omap-h63xx.git

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 46b2a8dc2ee..818b9a97e21 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -93,6 +93,7 @@
  */
 
 #define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -194,7 +195,8 @@
 #define CPU_AU1200		59
 #define CPU_34K			60
 #define CPU_PR4450		61
-#define CPU_LAST		61
+#define CPU_SB1A		62
+#define CPU_LAST		62
 
 /*
  * ISA Level encodings
@@ -202,16 +204,18 @@
  */
 #define MIPS_CPU_ISA_I		0x00000001
 #define MIPS_CPU_ISA_II		0x00000002
-#define MIPS_CPU_ISA_III	0x00008003
-#define MIPS_CPU_ISA_IV		0x00008004
-#define MIPS_CPU_ISA_V		0x00008005
-#define MIPS_CPU_ISA_M32	0x00000020
-#define MIPS_CPU_ISA_M64	0x00008040
+#define MIPS_CPU_ISA_III	0x00000004
+#define MIPS_CPU_ISA_IV		0x00000008
+#define MIPS_CPU_ISA_V		0x00000010
+#define MIPS_CPU_ISA_M32R1	0x00000020
+#define MIPS_CPU_ISA_M32R2	0x00000040
+#define MIPS_CPU_ISA_M64R1	0x00000080
+#define MIPS_CPU_ISA_M64R2	0x00000100
 
-/*
- * Bit 15 encodes if an ISA level supports 64-bit operations.
- */
-#define MIPS_CPU_ISA_64BIT	0x00008000
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
+	MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 
 /*
  * CPU Option encodings