X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-mips%2Fhazards.h;h=918a4894b587d10fe8450a96239ad42f0b7e63e5;hb=195be1c2086929efe1ca315e23f031f06e086369;hp=0fe02945feba0b8a18868126a99d977558294d33;hpb=3b9f6cb8a1ec791be79c6c7595fea922f12d1e64;p=linux-2.6-omap-h63xx.git diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 0fe02945feb..918a4894b58 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle * Copyright (C) MIPS Technologies, Inc. * written by Ralf Baechle */ @@ -23,6 +23,11 @@ static inline void name(void) \ __asm__ __volatile__ (#name); \ } +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + #endif ASMMACRO(_ssnop, @@ -52,6 +57,7 @@ ASMMACRO(tlb_probe_hazard, _ehb ) ASMMACRO(irq_enable_hazard, + _ehb ) ASMMACRO(irq_disable_hazard, _ehb @@ -157,7 +163,7 @@ ASMMACRO(back_to_back_c0_hazard, * processors. */ ASMMACRO(mtc0_tlbw_hazard, - nop + nop; nop ) ASMMACRO(tlbw_use_hazard, nop; nop; nop @@ -177,4 +183,36 @@ ASMMACRO(back_to_back_c0_hazard, #endif + +/* FPU hazards */ + +#if defined(CONFIG_CPU_SB1) +ASMMACRO(enable_fpu_hazard, + .set push; + .set mips64; + .set noreorder; + _ssnop; + bnezl $0,.+4; + _ssnop; + .set pop +) +ASMMACRO(disable_fpu_hazard, +) + +#elif defined(CONFIG_CPU_MIPSR2) +ASMMACRO(enable_fpu_hazard, + _ehb +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#else +ASMMACRO(enable_fpu_hazard, + nop; nop; nop; nop +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#endif + #endif /* _ASM_HAZARDS_H */