X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-mips%2Fmach-au1x00%2Fau1000.h;h=582acd8adb81fd17d77cef2defbe8a606ec9312b;hb=70ac4385a13f78bc478f26d317511893741b05bd;hp=ffcd0492eb3a00752bdc491a6b197feabe29aa85;hpb=2d32ffa44a5323fda147bd5b0723744a9163e37f;p=linux-2.6-omap-h63xx.git diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index ffcd0492eb3..582acd8adb8 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -35,7 +35,6 @@ #ifndef _AU1000_H_ #define _AU1000_H_ -#include #ifndef _LANGUAGE_ASSEMBLY @@ -60,59 +59,36 @@ void static inline au_sync_delay(int ms) mdelay(ms); } -void static inline au_writeb(u8 val, int reg) +void static inline au_writeb(u8 val, unsigned long reg) { *(volatile u8 *)(reg) = val; } -void static inline au_writew(u16 val, int reg) +void static inline au_writew(u16 val, unsigned long reg) { *(volatile u16 *)(reg) = val; } -void static inline au_writel(u32 val, int reg) +void static inline au_writel(u32 val, unsigned long reg) { *(volatile u32 *)(reg) = val; } -static inline u8 au_readb(unsigned long port) +static inline u8 au_readb(unsigned long reg) { - return (*(volatile u8 *)port); + return (*(volatile u8 *)reg); } -static inline u16 au_readw(unsigned long port) +static inline u16 au_readw(unsigned long reg) { - return (*(volatile u16 *)port); + return (*(volatile u16 *)reg); } -static inline u32 au_readl(unsigned long port) +static inline u32 au_readl(unsigned long reg) { - return (*(volatile u32 *)port); + return (*(volatile u32 *)reg); } -/* These next three functions should be a generic part of the MIPS - * kernel (with the 'au_' removed from the name) and selected for - * processors that support the instructions. - * Taken from PPC tree. -- Dan - */ -/* Return the bit position of the most significant 1 bit in a word */ -static __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm volatile ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips32\n\t" - "clz\t%0,%1\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (lz) - : "r" (x)); - - return 31 - lz; -} static __inline__ int au_ffz(unsigned int x) { @@ -181,26 +157,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MEM_SDSLEEP (0x0030) #define MEM_SDSMCKE (0x0034) -#ifndef ASSEMBLER -/*typedef volatile struct -{ - uint32 sdmode0; - uint32 sdmode1; - uint32 sdmode2; - uint32 sdaddr0; - uint32 sdaddr1; - uint32 sdaddr2; - uint32 sdrefcfg; - uint32 sdautoref; - uint32 sdwrmd0; - uint32 sdwrmd1; - uint32 sdwrmd2; - uint32 sdsleep; - uint32 sdsmcke; - -} AU1X00_SDRAM;*/ -#endif - /* * MEM_SDMODE register content definitions */ @@ -286,49 +242,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MEM_SDSREF (0x08D0) #define MEM_SDSLEEP MEM_SDSREF -#ifndef ASSEMBLER -/*typedef volatile struct -{ - uint32 sdmode0; - uint32 reserved0; - uint32 sdmode1; - uint32 reserved1; - uint32 sdmode2; - uint32 reserved2[3]; - uint32 sdaddr0; - uint32 reserved3; - uint32 sdaddr1; - uint32 reserved4; - uint32 sdaddr2; - uint32 reserved5[3]; - uint32 sdconfiga; - uint32 reserved6; - uint32 sdconfigb; - uint32 reserved7; - uint32 sdstat; - uint32 reserved8; - uint32 sderraddr; - uint32 reserved9; - uint32 sdstride0; - uint32 reserved10; - uint32 sdstride1; - uint32 reserved11; - uint32 sdstride2; - uint32 reserved12[3]; - uint32 sdwrmd0; - uint32 reserved13; - uint32 sdwrmd1; - uint32 reserved14; - uint32 sdwrmd2; - uint32 reserved15[11]; - uint32 sdprecmd; - uint32 reserved16; - uint32 sdautoref; - uint32 reserved17; - uint32 sdsref; - -} AU1550_SDRAM;*/ -#endif #endif /* @@ -365,9 +278,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define SYS_PHYS_ADDR 0x11900000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000 -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /********************************************************************/ @@ -399,13 +312,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 -#define PCI_MEM_PHYS_ADDR 0x400000000 -#define PCI_IO_PHYS_ADDR 0x500000000 -#define PCI_CONFIG0_PHYS_ADDR 0x600000000 -#define PCI_CONFIG1_PHYS_ADDR 0x680000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000 -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define PCI_MEM_PHYS_ADDR 0x400000000ULL +#define PCI_IO_PHYS_ADDR 0x500000000ULL +#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL +#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /********************************************************************/ @@ -442,9 +355,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define LCD_PHYS_ADDR 0x15000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000 -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /***********************************************************************/ @@ -473,13 +386,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define PSC1_PHYS_ADDR 0x11B00000 #define PSC2_PHYS_ADDR 0x10A00000 #define PSC3_PHYS_ADDR 0x10B00000 -#define PCI_MEM_PHYS_ADDR 0x400000000 -#define PCI_IO_PHYS_ADDR 0x500000000 -#define PCI_CONFIG0_PHYS_ADDR 0x600000000 -#define PCI_CONFIG1_PHYS_ADDR 0x680000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000 -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 +#define PCI_MEM_PHYS_ADDR 0x400000000ULL +#define PCI_IO_PHYS_ADDR 0x500000000ULL +#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL +#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /***********************************************************************/ @@ -500,15 +413,15 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define DDMA_PHYS_ADDR 0x14002000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000 -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 #define SD0_PHYS_ADDR 0x10600000 #define SD1_PHYS_ADDR 0x10680000 #define LCD_PHYS_ADDR 0x15000000 #define SWCNT_PHYS_ADDR 0x1110010C #define MAEFE_PHYS_ADDR 0x14012000 #define MAEBE_PHYS_ADDR 0x14010000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif @@ -924,6 +837,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap +#define USB_OHCI_LEN 0x00060000 #define USB_HOST_CONFIG 0xB4027ffc #define AU1550_ETH0_BASE 0xB0500000 @@ -1103,10 +1017,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define I2S_CONTROL_D (1<<1) #define I2S_CONTROL_CE (1<<0) -#ifndef CONFIG_SOC_AU1200 - /* USB Host Controller */ +#ifndef USB_OHCI_LEN #define USB_OHCI_LEN 0x00100000 +#endif + +#ifndef CONFIG_SOC_AU1200 /* USB Device Controller */ #define USBD_EP0RD 0xB0200000 @@ -1281,7 +1197,11 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* UARTS 0-3 */ #define UART_BASE UART0_ADDR +#ifdef CONFIG_SOC_AU1200 +#define UART_DEBUG_BASE UART1_ADDR +#else #define UART_DEBUG_BASE UART3_ADDR +#endif #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ @@ -1647,6 +1567,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_CS_MI2_MASK (0x7<