X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-sh%2Fmmu_context.h;h=87e812f68bb06d11c83b5ecca25b72d5cb35366b;hb=12e0036818eed243c8ed6583ebf98261a2554e12;hp=c7088efe579add81dae62e2a3dd54134b06fef3b;hpb=3b9f6cb8a1ec791be79c6c7595fea922f12d1e64;p=linux-2.6-omap-h63xx.git diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h index c7088efe579..87e812f68bb 100644 --- a/include/asm-sh/mmu_context.h +++ b/include/asm-sh/mmu_context.h @@ -1,30 +1,24 @@ /* * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2007 Paul Mundt * * ASID handling idea taken from MIPS implementation. */ #ifndef __ASM_SH_MMU_CONTEXT_H #define __ASM_SH_MMU_CONTEXT_H -#ifdef __KERNEL__ +#ifdef __KERNEL__ #include #include -#include #include #include +#include /* * The MMU "context" consists of two things: * (a) TLB cache version (or round, cycle whatever expression you like) * (b) ASID (Address Space IDentifier) */ - -/* - * Cache of MMU context last used. - */ -extern unsigned long mmu_context_cache; - #define MMU_CONTEXT_ASID_MASK 0x000000ff #define MMU_CONTEXT_VERSION_MASK 0xffffff00 #define MMU_CONTEXT_FIRST_VERSION 0x00000100 @@ -33,136 +27,119 @@ extern unsigned long mmu_context_cache; /* ASID is 8-bit value, so it can't be 0x100 */ #define MMU_NO_ASID 0x100 +#ifdef CONFIG_MMU +#define asid_cache(cpu) (cpu_data[cpu].asid_cache) +#define cpu_context(cpu, mm) ((mm)->context.id[cpu]) + +#define cpu_asid(cpu, mm) \ + (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK) + /* * Virtual Page Number mask */ #define MMU_VPN_MASK 0xfffff000 -#ifdef CONFIG_MMU +#if defined(CONFIG_SUPERH32) +#include "mmu_context_32.h" +#else +#include "mmu_context_64.h" +#endif + /* * Get MMU context if needed. */ -static __inline__ void -get_mmu_context(struct mm_struct *mm) +static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) { - extern void flush_tlb_all(void); - unsigned long mc = mmu_context_cache; + unsigned long asid = asid_cache(cpu); /* Check if we have old version of context. */ - if (((mm->context.id ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0) + if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) /* It's up to date, do nothing */ return; /* It's old, we need to get new context with new version. */ - mc = ++mmu_context_cache; - if (!(mc & MMU_CONTEXT_ASID_MASK)) { + if (!(++asid & MMU_CONTEXT_ASID_MASK)) { /* * We exhaust ASID of this version. * Flush all TLB and start new cycle. */ flush_tlb_all(); + +#ifdef CONFIG_SUPERH64 + /* + * The SH-5 cache uses the ASIDs, requiring both the I and D + * cache to be flushed when the ASID is exhausted. Weak. + */ + flush_cache_all(); +#endif + /* * Fix version; Note that we avoid version #0 * to distingush NO_CONTEXT. */ - if (!mc) - mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION; + if (!asid) + asid = MMU_CONTEXT_FIRST_VERSION; } - mm->context.id = mc; + + cpu_context(cpu, mm) = asid_cache(cpu) = asid; } /* * Initialize the context related info for a new mm_struct * instance. */ -static __inline__ int init_new_context(struct task_struct *tsk, - struct mm_struct *mm) +static inline int init_new_context(struct task_struct *tsk, + struct mm_struct *mm) { - mm->context.id = NO_CONTEXT; + int i; - return 0; -} + for (i = 0; i < num_online_cpus(); i++) + cpu_context(i, mm) = NO_CONTEXT; -/* - * Destroy context related info for an mm_struct that is about - * to be put to rest. - */ -static __inline__ void destroy_context(struct mm_struct *mm) -{ - /* Do nothing */ -} - -static __inline__ void set_asid(unsigned long asid) -{ - unsigned long __dummy; - - __asm__ __volatile__ ("mov.l %2, %0\n\t" - "and %3, %0\n\t" - "or %1, %0\n\t" - "mov.l %0, %2" - : "=&r" (__dummy) - : "r" (asid), "m" (__m(MMU_PTEH)), - "r" (0xffffff00)); -} - -static __inline__ unsigned long get_asid(void) -{ - unsigned long asid; - - __asm__ __volatile__ ("mov.l %1, %0" - : "=r" (asid) - : "m" (__m(MMU_PTEH))); - asid &= MMU_CONTEXT_ASID_MASK; - return asid; + return 0; } /* * After we have set current->mm to a new value, this activates * the context for the new mm so we see the new mappings. */ -static __inline__ void activate_context(struct mm_struct *mm) +static inline void activate_context(struct mm_struct *mm, unsigned int cpu) { - get_mmu_context(mm); - set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK); + get_mmu_context(mm, cpu); + set_asid(cpu_asid(cpu, mm)); } -/* MMU_TTB can be used for optimizing the fault handling. - (Currently not used) */ -static __inline__ void switch_mm(struct mm_struct *prev, - struct mm_struct *next, - struct task_struct *tsk) +static inline void switch_mm(struct mm_struct *prev, + struct mm_struct *next, + struct task_struct *tsk) { - if (likely(prev != next)) { - unsigned long __pgdir = (unsigned long)next->pgd; - - __asm__ __volatile__("mov.l %0, %1" - : /* no output */ - : "r" (__pgdir), "m" (__m(MMU_TTB))); - activate_context(next); - } -} - -#define deactivate_mm(tsk,mm) do { } while (0) + unsigned int cpu = smp_processor_id(); -#define activate_mm(prev, next) \ - switch_mm((prev),(next),NULL) - -static __inline__ void -enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ + if (likely(prev != next)) { + cpu_set(cpu, next->cpu_vm_mask); + set_TTB(next->pgd); + activate_context(next, cpu); + } else + if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) + activate_context(next, cpu); } -#else /* !CONFIG_MMU */ +#else #define get_mmu_context(mm) do { } while (0) #define init_new_context(tsk,mm) (0) #define destroy_context(mm) do { } while (0) #define set_asid(asid) do { } while (0) #define get_asid() (0) -#define activate_context(mm) do { } while (0) +#define cpu_asid(cpu, mm) ({ (void)cpu; 0; }) +#define switch_and_save_asid(asid) (0) +#define set_TTB(pgd) do { } while (0) +#define get_TTB() (0) +#define activate_context(mm,cpu) do { } while (0) #define switch_mm(prev,next,tsk) do { } while (0) +#endif /* CONFIG_MMU */ + +#define activate_mm(prev, next) switch_mm((prev),(next),NULL) #define deactivate_mm(tsk,mm) do { } while (0) -#define activate_mm(prev,next) do { } while (0) #define enter_lazy_tlb(mm,tsk) do { } while (0) -#endif /* CONFIG_MMU */ #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) /* @@ -172,14 +149,16 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) */ static inline void enable_mmu(void) { + unsigned int cpu = smp_processor_id(); + /* Enable MMU */ ctrl_outl(MMU_CONTROL_INIT, MMUCR); ctrl_barrier(); - if (mmu_context_cache == NO_CONTEXT) - mmu_context_cache = MMU_CONTEXT_FIRST_VERSION; + if (asid_cache(cpu) == NO_CONTEXT) + asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; - set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK); + set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); } static inline void disable_mmu(void) @@ -197,8 +176,8 @@ static inline void disable_mmu(void) * MMU control handlers for processors lacking memory * management hardware. */ -#define enable_mmu() do { BUG(); } while (0) -#define disable_mmu() do { BUG(); } while (0) +#define enable_mmu() do { } while (0) +#define disable_mmu() do { } while (0) #endif #endif /* __KERNEL__ */