X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-xtensa%2Fcache.h;h=3bba2a540cf087009415c58498dc06864336ab5f;hb=c36194871293100bd4b2ecb54ac9774d6e627aa2;hp=5aae3f12407c63914fcca297948d5fd2e9368ae0;hpb=aef7b83c92dd0b7e994805440655d1d64147287b;p=linux-2.6-omap-h63xx.git diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h index 5aae3f12407..3bba2a540cf 100644 --- a/include/asm-xtensa/cache.h +++ b/include/asm-xtensa/cache.h @@ -1,10 +1,9 @@ /* - * include/asm-xtensa/cacheflush.h + * include/asm-xtensa/cache.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * 2 of the License, or (at your option) any later version. * * (C) 2001 - 2005 Tensilica Inc. */ @@ -12,21 +11,23 @@ #ifndef _XTENSA_CACHE_H #define _XTENSA_CACHE_H -#include +#include -#if XCHAL_ICACHE_SIZE > 0 -# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif -#endif +#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH +#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) +#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) +#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) +#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) -#if XCHAL_DCACHE_SIZE > 0 -# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif +/* Maximum cache size per way. */ +#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE +# define CACHE_WAY_SIZE DCACHE_WAY_SIZE +#else +# define CACHE_WAY_SIZE ICACHE_WAY_SIZE #endif -#define L1_CACHE_SHIFT XCHAL_CACHE_LINEWIDTH_MAX -#define L1_CACHE_BYTES XCHAL_CACHE_LINESIZE_MAX #endif /* _XTENSA_CACHE_H */