X-Git-Url: http://pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Flinux%2Ffsl_devices.h;h=1831b196c70a9fe452fb37d605f8a8142b75e42d;hb=0ac49527318bc388a881152d60f49d7951606024;hp=abb64c437f6fd92b447deb18768549d7cbb45ddc;hpb=9cdf083f981b8d37b3212400a359368661385099;p=linux-2.6-omap-h63xx.git diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index abb64c437f6..1831b196c70 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -53,6 +53,7 @@ struct gianfar_platform_data { u32 bus_id; u32 phy_id; u8 mac_addr[6]; + phy_interface_t interface; }; struct gianfar_mdio_data { @@ -112,7 +113,7 @@ struct fsl_usb2_platform_data { struct fsl_spi_platform_data { u32 initial_spmode; /* initial SPMODE value */ u16 bus_num; - + bool qe_mode; /* board specific information */ u16 max_chipselect; void (*activate_cs)(u8 cs, u8 polarity); @@ -120,44 +121,10 @@ struct fsl_spi_platform_data { u32 sysclk; }; -/* Ethernet interface (phy management and speed) -*/ -enum enet_interface { - ENET_10_MII, /* 10 Base T, MII interface */ - ENET_10_RMII, /* 10 Base T, RMII interface */ - ENET_10_RGMII, /* 10 Base T, RGMII interface */ - ENET_100_MII, /* 100 Base T, MII interface */ - ENET_100_RMII, /* 100 Base T, RMII interface */ - ENET_100_RGMII, /* 100 Base T, RGMII interface */ - ENET_1000_GMII, /* 1000 Base T, GMII interface */ - ENET_1000_RGMII, /* 1000 Base T, RGMII interface */ - ENET_1000_TBI, /* 1000 Base T, TBI interface */ - ENET_1000_RTBI /* 1000 Base T, RTBI interface */ -}; - -struct ucc_geth_platform_data { - /* device specific information */ - u32 device_flags; - u32 phy_reg_addr; - - /* board specific information */ - u32 board_flags; - u8 rx_clock; - u8 tx_clock; - u32 phy_id; - enum enet_interface phy_interface; - u32 phy_interrupt; - u8 mac_addr[6]; +struct mpc8xx_pcmcia_ops { + void(*hw_ctrl)(int slot, int enable); + int(*voltage_set)(int slot, int vcc, int vpp); }; -/* Flags related to UCC Gigabit Ethernet device features */ -#define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001 -#define FSL_UGETH_DEV_HAS_COALESCE 0x00000002 -#define FSL_UGETH_DEV_HAS_RMON 0x00000004 - -/* Flags in ucc_geth_platform_data */ -#define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001 - /* if not set use a timer */ - #endif /* _FSL_DEVICE_H_ */ #endif /* __KERNEL__ */