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[ARM] mv78xx0: force eth2/eth3 to PHYless mode on pre-A0 silicon
authorLennert Buytenhek <buytenh@wantstofly.org>
Fri, 20 Feb 2009 01:31:58 +0000 (02:31 +0100)
committerNicolas Pitre <nico@cam.org>
Fri, 20 Feb 2009 03:41:37 +0000 (22:41 -0500)
commit712424fd95134bf88d27f3885389fe6ab13f34ac
tree8b146e05b2f2810bddd1c55f30764a690a534a7ftree | snapshot
parentcfdeb6376e439c58c2d37de492d2a8c763621022commit | diff
[ARM] mv78xx0: force eth2/eth3 to PHYless mode on pre-A0 silicon

On pre-A0 revisions of the mv78xx0 SoC, the third and fourth
ethernet interface are not brought out to pins, but are internally
cross-connected, so if we run on pre-A0 silicon, we'll force eth2
and eth3 to PHYless mode.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
arch/arm/mach-mv78xx0/common.c diff | blob | history
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