void t3_link_changed(struct adapter *adapter, int port_id);
 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
-int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
-int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
+int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
+int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
 int t3_seeprom_wp(struct adapter *adapter, int enable);
 int t3_get_tp_version(struct adapter *adapter, u32 *vers);
 int t3_check_tpsram_version(struct adapter *adapter, int *must_load);
 
 
        e->magic = EEPROM_MAGIC;
        for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
-               err = t3_seeprom_read(adapter, i, (u32 *) & buf[i]);
+               err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
 
        if (!err)
                memcpy(data, buf + e->offset, e->len);
 {
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adapter = pi->adapter;
-       u32 aligned_offset, aligned_len, *p;
+       u32 aligned_offset, aligned_len;
+       __le32 *p;
        u8 *buf;
        int err;
 
                buf = kmalloc(aligned_len, GFP_KERNEL);
                if (!buf)
                        return -ENOMEM;
-               err = t3_seeprom_read(adapter, aligned_offset, (u32 *) buf);
+               err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
                if (!err && aligned_len > 4)
                        err = t3_seeprom_read(adapter,
                                              aligned_offset + aligned_len - 4,
-                                             (u32 *) & buf[aligned_len - 4]);
+                                             (__le32 *) & buf[aligned_len - 4]);
                if (err)
                        goto out;
                memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
        if (err)
                goto out;
 
-       for (p = (u32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
+       for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
                err = t3_seeprom_write(adapter, aligned_offset, *p);
                aligned_offset += 4;
        }
 
  *     addres is written to the control register.  The hardware device will
  *     set the flag to 1 when 4 bytes have been read into the data register.
  */
-int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
+int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data)
 {
        u16 val;
        int attempts = EEPROM_MAX_POLL;
+       u32 v;
        unsigned int base = adapter->params.pci.vpd_cap_addr;
 
        if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
                CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
                return -EIO;
        }
-       pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, data);
-       *data = le32_to_cpu(*data);
+       pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v);
+       *data = cpu_to_le32(v);
        return 0;
 }
 
  *     Write a 32-bit word to a location in VPD EEPROM using the card's PCI
  *     VPD ROM capability.
  */
-int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
+int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data)
 {
        u16 val;
        int attempts = EEPROM_MAX_POLL;
                return -EINVAL;
 
        pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA,
-                              cpu_to_le32(data));
+                              le32_to_cpu(data));
        pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR,
                              addr | PCI_VPD_ADDR_F);
        do {
         * Card information is normally at VPD_BASE but some early cards had
         * it at 0.
         */
-       ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd);
+       ret = t3_seeprom_read(adapter, VPD_BASE, (__le32 *)&vpd);
        if (ret)
                return ret;
        addr = vpd.id_tag == 0x82 ? VPD_BASE : 0;
 
        for (i = 0; i < sizeof(vpd); i += 4) {
                ret = t3_seeprom_read(adapter, addr + i,
-                                     (u32 *)((u8 *)&vpd + i));
+                                     (__le32 *)((u8 *)&vpd + i));
                if (ret)
                        return ret;
        }
 {
        u32 csum;
        unsigned int i;
-       const u32 *p = (const u32 *)tp_sram;
+       const __be32 *p = (const __be32 *)tp_sram;
 
        /* Verify checksum */
        for (csum = 0, i = 0; i < size / sizeof(csum); i++)
 {
        u32 csum;
        unsigned int i;
-       const u32 *p = (const u32 *)fw_data;
+       const __be32 *p = (const __be32 *)fw_data;
        int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
 
        if ((size & 3) || size < FW_MIN_SIZE)
 int t3_set_proto_sram(struct adapter *adap, u8 *data)
 {
        int i;
-       u32 *buf = (u32 *)data;
+       __be32 *buf = (__be32 *)data;
 
        for (i = 0; i < PROTO_SRAM_LINES; i++) {
-               t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
-               t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
-               t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
-               t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
-               t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
+               t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++));
+               t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++));
+               t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++));
+               t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++));
+               t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++));
 
                t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
                if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))